}
if (mac_addr0) {
- memcpy(eap7660d_wmac0_mac, mac_addr0, sizeof(eap7660d_wmac0_mac));
+ memcpy(eap7660d_wmac0_mac, mac_addr0,
+ sizeof(eap7660d_wmac0_mac));
eap7660d_wmac0_data.macaddr = eap7660d_wmac0_mac;
}
if (mac_addr1) {
- memcpy(eap7660d_wmac1_mac, mac_addr1, sizeof(eap7660d_wmac1_mac));
+ memcpy(eap7660d_wmac1_mac, mac_addr1,
+ sizeof(eap7660d_wmac1_mac));
eap7660d_wmac1_data.macaddr = eap7660d_wmac1_mac;
}
nbg460n_gpio_buttons);
}
-MIPS_MACHINE(AR71XX_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", nbg460n_setup);
+MIPS_MACHINE(AR71XX_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH",
+ nbg460n_setup);
ar71xx_add_device_mdio(~RB450_MDIO_PHYMASK);
ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 1);
- ar71xx_eth0_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
+ ar71xx_eth0_data.phy_if_mode = (gige) ?
+ PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
ar71xx_eth0_data.phy_mask = RB450_LAN_PHYMASK;
ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 0);
- ar71xx_eth1_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
+ ar71xx_eth1_data.phy_if_mode = (gige) ?
+ PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
ar71xx_eth1_data.phy_mask = RB450_WAN_PHYMASK;
ar71xx_add_device_eth(1);
{
ubnt_generic_setup();
- ar71xx_add_device_mdio(~(UBNT_RSPRO_WAN_PHYMASK | UBNT_RSPRO_LAN_PHYMASK));
+ ar71xx_add_device_mdio(~(UBNT_RSPRO_WAN_PHYMASK |
+ UBNT_RSPRO_LAN_PHYMASK));
ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0);
ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
* if we set the BAR with proper base address
*/
if ((where == 0x10) && (size == 4)) {
- if (ar71xx_soc == AR71XX_SOC_AR7240)
- ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
- else
- ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0x1000ffff);
+ u32 val;
+ val = (ar71xx_soc == AR71XX_SOC_AR7240) ? 0xffff : 0x1000ffff;
+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, val);
}
return PCIBIOS_SUCCESSFUL;
return -ENODEV;
}
- if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) {
+ if (ar71xx_soc == AR71XX_SOC_AR7241 ||
+ ar71xx_soc == AR71XX_SOC_AR7242) {
t = __raw_readl(base + AR724X_PCI_REG_APP);
t |= BIT(16);
__raw_writel(t, base + AR724X_PCI_REG_APP);
goto free_hdr;
}
- kernel_len = le32_to_cpu(theader->offsets[1]) + sizeof(struct cybertan_header);
+ kernel_len = le32_to_cpu(theader->offsets[1]) +
+ sizeof(struct cybertan_header);
trx_parts[0].name = "u-boot";
trx_parts[0].offset = 0;
trx_parts[2].name = "rootfs";
trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size;
- trx_parts[2].size = master->size - 6 * master->erasesize - trx_parts[1].size;
+ trx_parts[2].size = master->size - 6 * master->erasesize -
+ trx_parts[1].size;
trx_parts[2].mask_flags = 0;
trx_parts[3].name = "nvram";
ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
if (ver != 1) {
- pr_err("%s: unsupported chip, ctrl=%08x\n", ag->dev->name, ctrl);
+ pr_err("%s: unsupported chip, ctrl=%08x\n",
+ ag->dev->name, ctrl);
return NULL;
}
}
for (i = 0; i < size; i++) {
- ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size];
+ int idx = i * ring->desc_size;
+ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
DBG("ag71xx: ring %p, desc %d at %p\n",
ring, i, ring->buf[i].desc);
}
rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
VSC73XX_ICPU_SRAM, &curVal);
if (rc) {
- dev_err(&spi->dev, "could not read microcode %d\n",rc);
+ dev_err(&spi->dev, "could not read microcode %d\n",
+ rc);
goto out;
}
max_timeout = (0xfffffffful / ar71xx_ahb_freq);
wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT;
- boot_status =
- (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) ?
- WDIOF_CARDRESET : 0;
+ if (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET)
+ boot_status = WDIOF_CARDRESET;
ret = misc_register(&ar71xx_wdt_miscdev);
if (ret)