apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
}
+ /*
+ * Setup extended LVT, AMD specific (K8, family 10h)
+ *
+ * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
+ * MCE interrupts are supported. Thus MCE offset must be set to 0.
++ *
++ * If mask=1, the LVT entry does not generate interrupts while mask=0
++ * enables the vector. See also the BKDGs.
+ */
+
+ #define APIC_EILVT_LVTOFF_MCE 0
+ #define APIC_EILVT_LVTOFF_IBS 1
+
+ static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
+ {
+ unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
+ unsigned int v = (mask << 16) | (msg_type << 8) | vector;
+
+ apic_write(reg, v);
+ }
+
+ u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
+ {
+ setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
+ return APIC_EILVT_LVTOFF_MCE;
+ }
+
+ u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
+ {
+ setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
+ return APIC_EILVT_LVTOFF_IBS;
+ }
++EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
+
/*
* Program the next event, relative to now
*/
return -ENODEV;
}
- init_sysfs();
+ #ifdef CONFIG_SMP
+ register_cpu_notifier(&oprofile_cpu_nb);
+ #endif
- using_nmi = 1;
+ /* default values, can be overwritten by model */
ops->create_files = nmi_create_files;
ops->setup = nmi_setup;
ops->shutdown = nmi_shutdown;
void op_nmi_exit(void)
{
- if (using_nmi)
+ if (using_nmi) {
exit_sysfs();
+ #ifdef CONFIG_SMP
+ unregister_cpu_notifier(&oprofile_cpu_nb);
+ #endif
+ }
+ if (model->exit)
+ model->exit();
}