arm: spear: enable SSP1, 2 and 3 clocks when SPI controller driver is built
authorQuentin Schulz <quentin.schulz@bootlin.com>
Fri, 31 Aug 2018 14:28:30 +0000 (16:28 +0200)
committerTom Rini <trini@konsulko.com>
Wed, 26 Sep 2018 01:49:18 +0000 (21:49 -0400)
SPI controllers SSP1, 2 and 3 require to enable their respective clocks.
Let's enable them only when the SPI controller driver is built.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
arch/arm/cpu/arm926ejs/spear/cpu.c
arch/arm/include/asm/arch-spear/spr_misc.h

index 88a40c6036020a85a6ea66eaa44eff9f209fd03e..51c4a730f4072ae8deaea94f8f23753570ad9aa0 100644 (file)
@@ -52,6 +52,9 @@ int arch_cpu_init(void)
 #if defined(CONFIG_SPEAR_GPIO)
        periph1_clken |= MISC_GPIO3ENB | MISC_GPIO4ENB;
 #endif
+#if defined(CONFIG_PL022_SPI)
+       periph1_clken |= MISC_SSP1ENB | MISC_SSP2ENB | MISC_SSP3ENB;
+#endif
 
        writel(periph1_clken, &misc_p->periph1_clken);
 
index 65063fca511871e49ad4d4c65379faf1e48d8f73..01b4b2bee308799d9a7ed1e3ba6c7d659e52ff1a 100644 (file)
@@ -146,11 +146,13 @@ struct misc_regs {
 #define MISC_SMIENB                    0x00200000
 #define MISC_GPIO3ENB                  0x00040000
 #define MISC_GPT3ENB                   0x00010000
+#define MISC_SSP3ENB                   0x00004000
 #define MISC_GPIO4ENB                  0x00002000
 #define MISC_GPT2ENB                   0x00000800
 #define MISC_FSMCENB                   0x00000200
 #define MISC_I2CENB                    0x00000080
 #define MISC_SSP2ENB                   0x00000070
+#define MISC_SSP1ENB                   0x00000020
 #define MISC_UART0ENB                  0x00000008
 
 /*   PERIPH_CLK_CFG   */