Tegra186: enable support for simulation environment

The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/disable - MCE firmware version checking is disabled and limited
Memory Controller settings are enabled

Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 798dbfa18c84136a858b00fb2086cd898567f604..2fb9b99f34a8e896859752d72db903541e216b75 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -495,7 +495,7 @@ void tegra_memctrl_setup(void)
        uint32_t num_overrides = sizeof(streamid_overrides) / sizeof(uint32_t);
        uint32_t num_sec_cfgs = sizeof(sec_cfgs) / sizeof(mc_streamid_security_cfg_t);
        uint32_t num_txn_overrides = sizeof(mc_override_cfgs) / sizeof(mc_txn_override_cfg_t);
-       uint32_t tegra_rev;
+       uint32_t chip_minor, chip_major;
        int i;
 
        INFO("Tegra Memory Controller (v2)\n");
@@ -543,10 +543,12 @@ void tegra_memctrl_setup(void)
        /*
         * Set the MC_TXN_OVERRIDE registers for write clients.
         */
-       tegra_rev = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) &
-                       HARDWARE_MINOR_REVISION_MASK) >> HARDWARE_MINOR_REVISION_SHIFT;
+       chip_major = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) >>
+                       MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK;
+       chip_minor = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) >>
+                       MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
 
-       if (tegra_rev == HARDWARE_REVISION_A01) {
+       if ((chip_major == 0) || (chip_major > 0 && chip_minor == 1)) {
 
                /* GPU and NVENC settings for rev. A01 */
                val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 04a7d0b3b768acf3974f6c1fef48f556381a93a6..7f618bdd3097cca976b357e0340cdead1715ff9d 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -78,9 +78,11 @@
  ******************************************************************************/
 #define TEGRA_MISC_BASE                        0x00100000
 #define  HARDWARE_REVISION_OFFSET      0x4
-#define  HARDWARE_MINOR_REVISION_MASK  0xf0000
-#define  HARDWARE_MINOR_REVISION_SHIFT 0x10
-#define  HARDWARE_REVISION_A01         1
+#define  MAJOR_VERSION_SHIFT           0x4
+#define  MAJOR_VERSION_MASK            0xF
+#define  MINOR_VERSION_SHIFT           0x10
+#define  MINOR_VERSION_MASK            0xF
+
 #define  MISCREG_PFCFG                 0x200C
 
 /*******************************************************************************

diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index 0e550f5ba3881867aa4700d10be9077a3a9157cb..9d0d71fd652497295d8f52e92bbfda71df8f2b29 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -457,7 +457,7 @@ void mce_verify_firmware_version(void)
        arch_mce_ops_t *ops;
        uint32_t cpu_ari_base;
        uint64_t version;
-       uint32_t major, minor;
+       uint32_t major, minor, chip_minor, chip_major;
 
        /* get a pointer to the CPU's arch_mce_ops_t struct */
        ops = mce_get_curr_cpu_ops();
@@ -476,6 +476,17 @@ void mce_verify_firmware_version(void)
        INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
                TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR);
 
+       /*
+        * MCE firmware is not running on simulation platforms. Simulation
+        * platforms are identified by v0.3 from the Tegra Chip ID value.
+        */
+       chip_major = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) >>
+                       MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK;
+       chip_minor = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) >>
+                       MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
+       if ((chip_major == 0) && (chip_minor == 3))
+               return;
+
        /*
         * Verify that the MCE firmware version and the interface header
         * match