drm/amdgpu/vcn:Update DPG mode VCN global tiling registers

Update Dynamic Power Gate mode VCN global tiling registers

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 0f3597c221c767f948a4ad7c945584ddaa0f7009..de57e6d697223f4734d0152d71e05dc377904d3a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -371,16 +371,27 @@ static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
                             0xFFFFFFFF, 0);
 
+       /* VCN global tiling registers */
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
                        adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
                        adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
        WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
                        adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
-       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
-                       adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
-       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
-                       adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
+       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
+       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
+       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
+       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
+       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
+       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
+       WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
+               adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 }
 
 /**