armada100: define CONFIG_SYS_CACHELINE_SIZE

By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>

diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
index d2094e5303a55256d2a9c40a8e4b29f26c652508..637f3130efb556d98f9decc66be57867dd6f8305 100644 (file)
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -33,6 +33,8 @@
 
 #include <asm/arch/armada100.h>
 #define CONFIG_ARM926EJS       1       /* Basic Architecture */
+/* default Dcache Line length for armada100 */
+#define CONFIG_SYS_CACHELINE_SIZE       32
 
 #define CONFIG_SYS_TCLK                (14745600)      /* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK    (3250000)       /* Timer Freq. 3.25MHZ */