powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA

A set of accessor functions was added to be able to access not only
memory mapped FPGA in a generic way.

Thanks to Wolfgang Denk for getting this sorted properly.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index f0df2e39e6a9159c5a2641d66cd40ccc9dc2cd66..426dc05c7d3cea53fda73193e25a3a2e40007aa2 100644 (file)
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -18,6 +18,12 @@
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int get_fpga_state(unsigned dev)
@@ -90,23 +96,17 @@ int board_early_init_r(void)
        gd405ep_set_fpga_reset(0);
 
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-               struct ihs_fpga *fpga =
-                       (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-               u16 *reflection_target = &fpga->reflection_low;
-#else
-               u16 *reflection_target = &fpga->reflection_high;
-#endif
                /*
                 * wait for fpga out of reset
                 */
                ctr = 0;
                while (1) {
-                       out_le16(&fpga->reflection_low,
-                               REFLECTION_TESTPATTERN);
+                       u16 val;
+
+                       FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
 
-                       if (in_le16(reflection_target) ==
-                               REFLECTION_TESTPATTERN_INV)
+                       FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+                       if (val == REFLECTION_TESTPATTERN_INV)
                                break;
 
                        udelay(100000);

diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index 48d878643bf275c9b95c7d9de1d9700b42953369..35dfbbc577aa9c6864017a2831257baf36192fa3 100644 (file)
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -55,6 +55,8 @@ enum {
        RAM_DDR2_64 = 2,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 int misc_init_r(void)
 {
        /* startup fans */
@@ -79,10 +81,9 @@ static unsigned int get_mc2_present(void)
 
 static void print_fpga_info(unsigned dev)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
-       u16 versions = in_le16(&fpga->versions);
-       u16 fpga_version = in_le16(&fpga->fpga_version);
-       u16 fpga_features = in_le16(&fpga->fpga_features);
+       u16 versions;
+       u16 fpga_version;
+       u16 fpga_features;
        unsigned unit_type;
        unsigned hardware_version;
        unsigned feature_rs232;
@@ -96,6 +97,10 @@ static void print_fpga_info(unsigned dev)
 
        printf("FPGA%d: ", dev);
 
+       FPGA_GET_REG(dev, versions, &versions);
+       FPGA_GET_REG(dev, fpga_version, &fpga_version);
+       FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
        hardware_version = versions & 0x000f;
 
        if (fpga_state
@@ -247,8 +252,9 @@ int checkboard(void)
 
 int last_stage_init(void)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-       u16 versions = in_le16(&fpga->versions);
+       u16 versions;
+
+       FPGA_GET_REG(0, versions, &versions);
 
        print_fpga_info(0);
        if (get_mc2_present())

diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index eee9ba0aaa15c8b809a84f30c17892c5fe97d471..03d796cdb89b1b09eb9662328ea862341629d3a9 100644 (file)
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -37,6 +37,8 @@ enum {
        HWVER_122 = 3,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 int misc_init_r(void)
 {
        /* startup fans */
@@ -101,15 +103,18 @@ int checkboard(void)
 
 static void print_fpga_info(void)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-       u16 versions = in_le16(&fpga->versions);
-       u16 fpga_version = in_le16(&fpga->fpga_version);
-       u16 fpga_features = in_le16(&fpga->fpga_features);
+       u16 versions;
+       u16 fpga_version;
+       u16 fpga_features;
        unsigned unit_type;
        unsigned hardware_version;
        unsigned feature_channels;
        unsigned feature_expansion;
 
+       FPGA_GET_REG(0, versions, &versions);
+       FPGA_GET_REG(0, fpga_version, &fpga_version);
+       FPGA_GET_REG(0, fpga_features, &fpga_features);
+
        unit_type = (versions & 0xf000) >> 12;
        hardware_version = versions & 0x000f;
        feature_channels = fpga_features & 0x007f;
@@ -163,7 +168,6 @@ static void print_fpga_info(void)
  */
 int last_stage_init(void)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
        unsigned int k;
 
        print_fpga_info();
@@ -175,7 +179,7 @@ int last_stage_init(void)
                configure_gbit_phy(k);
 
        /* take fpga serdes blocks out of reset */
-       out_le16(&fpga->quad_serdes_reset, 0);
+       FPGA_SET_REG(0, quad_serdes_reset, 0);
 
        return 0;
 }

diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index c728bc7b73accde0d68827e80dccbe4d6280b724..1af5245c8afc7a14c061d4d1419dce0dcdbad51e 100644 (file)
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -53,6 +53,8 @@ enum {
        RAM_DDR2_32 = 0,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 /*
  * Check Board Identity:
  */
@@ -76,10 +78,9 @@ int checkboard(void)
 
 static void print_fpga_info(void)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-       u16 versions = in_le16(&fpga->versions);
-       u16 fpga_version = in_le16(&fpga->fpga_version);
-       u16 fpga_features = in_le16(&fpga->fpga_features);
+       u16 versions;
+       u16 fpga_version;
+       u16 fpga_features;
        unsigned unit_type;
        unsigned hardware_version;
        unsigned feature_compression;
@@ -90,6 +91,10 @@ static void print_fpga_info(void)
        unsigned feature_carriers;
        unsigned feature_video_channels;
 
+       FPGA_GET_REG(0, versions, &versions);
+       FPGA_GET_REG(0, fpga_version, &fpga_version);
+       FPGA_GET_REG(0, fpga_features, &fpga_features);
+
        unit_type = (versions & 0xf000) >> 12;
        hardware_version = versions & 0x000f;
        feature_compression = (fpga_features & 0xe000) >> 13;
@@ -211,20 +216,25 @@ int last_stage_init(void)
 
 /*
  * provide access to fpga gpios (for I2C bitbang)
+ * (these may look all too simple but make iocon.h much more readable)
  */
 void fpga_gpio_set(int pin)
 {
-       out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
+       FPGA_SET_REG(0, gpio.set, pin);
 }
 
 void fpga_gpio_clear(int pin)
 {
-       out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
+       FPGA_SET_REG(0, gpio.clear, pin);
 }
 
 int fpga_gpio_get(int pin)
 {
-       return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
+       u16 val;
+
+       FPGA_GET_REG(0, gpio.read, &val);
+
+       return val & pin;
 }
 
 void gd405ep_init(void)

diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c
index bca78032f8158114b3bd2888dc9acac7a9a8cfc6..ff0edb2547967944523599d103ea2f8eb1b5250a 100644 (file)
--- a/board/gdsys/405ep/neo.c
+++ b/board/gdsys/405ep/neo.c
@@ -28,6 +28,8 @@ enum {
        HWVER_300 = 3,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 int misc_init_r(void)
 {
        /* startup fans */
@@ -54,10 +56,9 @@ int checkboard(void)
 
 static void print_fpga_info(void)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-       u16 versions = in_le16(&fpga->versions);
-       u16 fpga_version = in_le16(&fpga->fpga_version);
-       u16 fpga_features = in_le16(&fpga->fpga_features);
+       u16 versions;
+       u16 fpga_version;
+       u16 fpga_features;
        int fpga_state = get_fpga_state(0);
        unsigned unit_type;
        unsigned hardware_version;
@@ -74,6 +75,10 @@ static void print_fpga_info(void)
                return;
        }
 
+       FPGA_GET_REG(0, versions, &versions);
+       FPGA_GET_REG(0, fpga_version, &fpga_version);
+       FPGA_GET_REG(0, fpga_features, &fpga_features);
+
        unit_type = (versions & 0xf000) >> 12;
        hardware_version = versions & 0x000f;
        feature_channels = fpga_features & 0x007f;

diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c
index 32e24c08cb9ce8340f589ab21d1772ef61bea087..c1a583ffbe09fcbb80e0af44401b4e9931814e80 100644 (file)
--- a/board/gdsys/405ex/405ex.c
+++ b/board/gdsys/405ex/405ex.c
@@ -11,6 +11,12 @@
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int get_fpga_state(unsigned dev)
@@ -220,23 +226,17 @@ int board_early_init_r(void)
        gd405ex_set_fpga_reset(0);
 
        for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-               struct ihs_fpga *fpga =
-                       (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-               u16 *reflection_target = &fpga->reflection_low;
-#else
-               u16 *reflection_target = &fpga->reflection_high;
-#endif
                /*
                 * wait for fpga out of reset
                 */
                ctr = 0;
                while (1) {
-                       out_le16(&fpga->reflection_low,
-                               REFLECTION_TESTPATTERN);
+                       u16 val;
+
+                       FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
 
-                       if (in_le16(reflection_target) ==
-                               REFLECTION_TESTPATTERN_INV)
+                       FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+                       if (val == REFLECTION_TESTPATTERN_INV)
                                break;
 
                        udelay(100000);

diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index fa8961a35177a78cd9de65b4596166a5554862bd..2f8e306261815acd00e51137c31d2034acf34b4b 100644 (file)
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -51,6 +51,8 @@ enum {
        HWVER_110 = 1,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 static inline void blank_string(int size)
 {
        int i;
@@ -84,10 +86,9 @@ int misc_init_r(void)
 
 static void print_fpga_info(unsigned dev)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
-       u16 versions = in_le16(&fpga->versions);
-       u16 fpga_version = in_le16(&fpga->fpga_version);
-       u16 fpga_features = in_le16(&fpga->fpga_features);
+       u16 versions;
+       u16 fpga_version;
+       u16 fpga_features;
        int fpga_state = get_fpga_state(dev);
 
        unsigned unit_type;
@@ -95,6 +96,10 @@ static void print_fpga_info(unsigned dev)
        unsigned feature_channels;
        unsigned feature_expansion;
 
+       FPGA_GET_REG(dev, versions, &versions);
+       FPGA_GET_REG(dev, fpga_version, &fpga_version);
+       FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
        printf("FPGA%d: ", dev);
        if (fpga_state & FPGA_STATE_PLATFORM)
                printf("(legacy) ");
@@ -226,8 +231,6 @@ int last_stage_init(void)
 {
        unsigned int k;
        unsigned int fpga;
-       struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-       struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
        int failed = 0;
        char str_phys[] = "Setup PHYs -";
        char str_serdes[] = "Start SERDES blocks";
@@ -265,17 +268,16 @@ int last_stage_init(void)
        /* take fpga serdes blocks out of reset */
        puts(str_serdes);
        udelay(500000);
-       out_le16(&fpga0->quad_serdes_reset, 0);
-       out_le16(&fpga1->quad_serdes_reset, 0);
+       FPGA_SET_REG(0, quad_serdes_reset, 0);
+       FPGA_SET_REG(1, quad_serdes_reset, 0);
        blank_string(strlen(str_serdes));
 
        /* take channels out of reset */
        puts(str_channels);
        udelay(500000);
        for (fpga = 0; fpga < 2; ++fpga) {
-               u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
                for (k = 0; k < 32; ++k)
-                       out_le16(ch0_config_int + 4 * k, 0);
+                       FPGA_SET_REG(fpga, ch[k].config_int, 0);
        }
        blank_string(strlen(str_channels));
 
@@ -283,16 +285,16 @@ int last_stage_init(void)
        puts(str_locks);
        udelay(500000);
        for (fpga = 0; fpga < 2; ++fpga) {
-               u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
                for (k = 0; k < 32; ++k) {
-                       u16 status = in_le16(ch0_status_int + 4*k);
+                       u16 status;
+                       FPGA_GET_REG(k, ch[k].status_int, &status);
                        if (!(status & (1 << 4))) {
                                failed = 1;
                                printf("fpga %d channel %d: no serdes lock\n",
                                        fpga, k);
                        }
                        /* reset events */
-                       out_le16(ch0_status_int + 4*k, status);
+                       FPGA_SET_REG(fpga, ch[k].status_int, 0);
                }
        }
        blank_string(strlen(str_locks));
@@ -300,14 +302,14 @@ int last_stage_init(void)
        /* verify hicb_status */
        puts(str_hicb);
        for (fpga = 0; fpga < 2; ++fpga) {
-               u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int;
                for (k = 0; k < 32; ++k) {
-                       u16 status = in_le16(ch0_hicb_status_int + 4*k);
+                       u16 status;
+                       FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
                        if (status)
                                printf("fpga %d hicb %d: hicb status %04x\n",
                                        fpga, k, status);
                        /* reset events */
-                       out_le16(ch0_hicb_status_int + 4*k, status);
+                       FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
                }
        }
        blank_string(strlen(str_hicb));

diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 43e6a4cdefbd99981fcb420f627a4016313bb841..60b16048b93965628305673fc906eb80a77dde99 100644 (file)
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -13,6 +13,8 @@ endif
 
 LIB    = $(obj)lib$(VENDOR).o
 
+COBJS-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
+
 COBJS-$(CONFIG_IO) += miiphybb.o
 COBJS-$(CONFIG_IO64) += miiphybb.o
 COBJS-$(CONFIG_IOCON) += osd.o

diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c
new file mode 100644 (file)
index 0000000..e3af6cb
--- /dev/null
+++ b/board/gdsys/common/fpga.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <gdsys_fpga.h>
+
+#include <asm/io.h>
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+       out_le16(reg, data);
+
+       return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+       *data = in_le16(reg);
+
+       return 0;
+}

diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 45cea5eaaf350153866008cab1bf9b3addd372e4..fd84388f8969bcd2ee41605650687ff7de59df52 100644 (file)
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -6,8 +6,8 @@
  */
 
 #include <common.h>
-#include <i2c.h>
 #include <asm/io.h>
+#include <i2c.h>
 
 #include <gdsys_fpga.h>
 
@@ -54,34 +54,41 @@ enum {
 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
-       struct ihs_i2c *i2c = &fpga->i2c;
+       u16 val;
 
-       while (in_le16(&fpga->extended_interrupt) & (1 << 12))
-               ;
-       out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
-       out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
+       do {
+               FPGA_GET_REG(screen, extended_interrupt, &val);
+       } while (val & (1 << 12));
+
+       FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
+       FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
 }
 
 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
-       struct ihs_i2c *i2c = &fpga->i2c;
        unsigned int ctr = 0;
+       u16 val;
+
+       do {
+               FPGA_GET_REG(screen, extended_interrupt, &val);
+       } while (val & (1 << 12));
 
-       while (in_le16(&fpga->extended_interrupt) & (1 << 12))
-               ;
-       out_le16(&fpga->extended_interrupt, 1 << 14);
-       out_le16(&i2c->write_mailbox_ext, reg);
-       out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
-       while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
+       FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
+       FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
+       FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
+
+       FPGA_GET_REG(screen, extended_interrupt, &val);
+       while (!(val & (1 << 14))) {
                udelay(100000);
                if (ctr++ > 5) {
                        printf("iic receive timeout\n");
                        break;
                }
+               FPGA_GET_REG(screen, extended_interrupt, &val);
        }
-       return in_le16(&i2c->read_mailbox_ext) >> 8;
+
+       FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
+       return val >> 8;
 }
 #endif
 
@@ -113,7 +120,6 @@ static void mpc92469ac_calc_parameters(unsigned int fout,
 
 static void mpc92469ac_set(unsigned screen, unsigned int fout)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
        unsigned int n;
        unsigned int m;
        unsigned int bitval = 0;
@@ -134,7 +140,7 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout)
                break;
        }
 
-       out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
+       FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
 }
 #endif
 
@@ -249,14 +255,12 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
 static int osd_write_videomem(unsigned screen, unsigned offset,
        u16 *data, size_t charcount)
 {
-       struct ihs_fpga *fpga =
-               (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen);
        unsigned int k;
 
        for (k = 0; k < charcount; ++k) {
                if (offset + k >= BUFSIZE)
                        return -1;
-               out_le16(&fpga->videomem + offset + k, data[k]);
+               FPGA_SET_REG(screen, videomem[offset + k], data[k]);
        }
 
        return charcount;
@@ -302,14 +306,15 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int osd_probe(unsigned screen)
 {
-       struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
-       struct ihs_osd *osd = &fpga->osd;
-       u16 version = in_le16(&osd->version);
-       u16 features = in_le16(&osd->features);
+       u16 version;
+       u16 features;
        unsigned width;
        unsigned height;
        u8 value;
 
+       FPGA_GET_REG(0, osd.version, &version);
+       FPGA_GET_REG(0, osd.features, &features);
+
        width = ((features & 0x3f00) >> 8) + 1;
        height = (features & 0x001f) + 1;
 
@@ -356,12 +361,13 @@ int osd_probe(unsigned screen)
        fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
 #endif
 
-       out_le16(&fpga->videocontrol, 0x0002);
-       out_le16(&osd->control, 0x0049);
+       FPGA_SET_REG(screen, videocontrol, 0x0002);
+       FPGA_SET_REG(screen, osd.control, 0x0049);
+
+       FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
+       FPGA_SET_REG(screen, osd.x_pos, 0x007f);
+       FPGA_SET_REG(screen, osd.y_pos, 0x005f);
 
-       out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
-       out_le16(&osd->x_pos, 0x007f);
-       out_le16(&osd->y_pos, 0x005f);
 
        return 0;
 }

diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 17391cddc988529c2f1314125f61a443a4ea45b9..d4011a1e8ac8b240cf2d27d7f8806e0995a4abf4 100644 (file)
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -123,6 +123,12 @@
 
 #define CONFIG_SYS_FPGA_COUNT          2
 
+#define CONFIG_SYS_FPGA_PTR { \
+       (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+       (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 #define CONFIG_SYS_LATCH0_RESET                0xffff
 #define CONFIG_SYS_LATCH0_BOOT         0xffff
 #define CONFIG_SYS_LATCH1_RESET                0xffcf

diff --git a/include/configs/io.h b/include/configs/io.h
index 33743e61ac0951b7e655d28daafcffa8dc463f7d..27d1b0f0a1be5161c88819408252e04959ca8fa7 100644 (file)
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -230,6 +230,11 @@
 
 #define CONFIG_SYS_FPGA_COUNT          1
 
+#define CONFIG_SYS_FPGA_PTR \
+       { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE          0x7f200000
 #define CONFIG_SYS_EBC_PB3AP           0xa2015480

diff --git a/include/configs/io64.h b/include/configs/io64.h
index dcd1b82e25f0ffd738049d33240a577b687de07c..f110b706020f73fc01d6dee5a2f7497c5ece9e8f 100644 (file)
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -498,6 +498,12 @@
 
 #define CONFIG_SYS_FPGA_COUNT          2
 
+#define CONFIG_SYS_FPGA_PTR { \
+       (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+       (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 #define CONFIG_SYS_LATCH0_RESET                0xffff
 #define CONFIG_SYS_LATCH0_BOOT         0xffff
 #define CONFIG_SYS_LATCH1_RESET                0xffbf

diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 32d9050adb952f14838e96ba00ed4ac5ba00f28e..67a7ab9ee3b356775104d54220707b7b9546343e 100644 (file)
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -236,6 +236,11 @@ int fpga_gpio_get(int pin);
 
 #define CONFIG_SYS_FPGA_COUNT          1
 
+#define CONFIG_SYS_FPGA_PTR \
+       { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE          0x7f200000
 #define CONFIG_SYS_EBC_PB3AP           0x02025080

diff --git a/include/configs/neo.h b/include/configs/neo.h
index 5abb8b1a7521d822ecd87513f13ce29fc78af40b..91871f718f417e52a9ba863c9e25d578bda51644 100644 (file)
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -222,6 +222,11 @@
 
 #define CONFIG_SYS_FPGA_COUNT          1
 
+#define CONFIG_SYS_FPGA_PTR \
+       { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 /* Memory Bank 3 (Latches) initialization                      */
 #define CONFIG_SYS_LATCH_BASE          0x7f200000
 #define CONFIG_SYS_EBC_PB3AP           0x92015480

diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 0a8268cbb581ec060a6ab7f5af578488d4129429..8b895457bd74c077e4921b92f52b10da61b6ddec 100644 (file)
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -19,6 +19,23 @@ enum {
 int get_fpga_state(unsigned dev);
 void print_fpga_state(unsigned dev);
 
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
+
+extern struct ihs_fpga *fpga_ptr[];
+
+#define FPGA_SET_REG(ix, fld, val) \
+       fpga_set_reg((ix), \
+                    &fpga_ptr[ix]->fld, \
+                    offsetof(struct ihs_fpga, fld), \
+                    val)
+
+#define FPGA_GET_REG(ix, fld, val) \
+       fpga_get_reg((ix), \
+                    &fpga_ptr[ix]->fld, \
+                    offsetof(struct ihs_fpga, fld), \
+                    val)
+
 struct ihs_gpio {
        u16 read;
        u16 clear;
@@ -67,6 +84,19 @@ struct ihs_fpga {
 #endif
 
 #ifdef CONFIG_IO64
+
+struct ihs_fpga_channel {
+       u16 status_int;
+       u16 config_int;
+       u16 switch_connect_config;
+       u16 tx_destination;
+};
+
+struct ihs_fpga_hicb {
+       u16 status_int;
+       u16 config_int;
+};
+
 struct ihs_fpga {
        u16 reflection_low;     /* 0x0000 */
        u16 versions;           /* 0x0002 */
@@ -75,12 +105,9 @@ struct ihs_fpga {
        u16 reserved_0[5];      /* 0x0008 */
        u16 quad_serdes_reset;  /* 0x0012 */
        u16 reserved_1[502];    /* 0x0014 */
-       u16 ch0_status_int;     /* 0x0400 */
-       u16 ch0_config_int;     /* 0x0402 */
-       u16 reserved_2[126];    /* 0x0404 */
-       u16 ch0_hicb_status_int;/* 0x0500 */
-       u16 ch0_hicb_config_int;/* 0x0502 */
-       u16 reserved_3[7549];   /* 0x0504 */
+       struct ihs_fpga_channel ch[32];         /* 0x0400 */
+       struct ihs_fpga_channel hicb_ch[32];    /* 0x0500 */
+       u16 reserved_2[7487];   /* 0x0580 */
        u16 reflection_high;    /* 0x3ffe */
 };
 #endif
@@ -100,7 +127,7 @@ struct ihs_fpga {
        u16 reflection_high;    /* 0x00fe */
        struct ihs_osd osd;     /* 0x0100 */
        u16 reserved_3[889];    /* 0x010e */
-       u16 videomem;           /* 0x0800 */
+       u16 videomem[31736];    /* 0x0800 */
 };
 #endif
 
@@ -121,7 +148,7 @@ struct ihs_fpga {
        u16 reserved_4[176];    /* 0x00a0 */
        struct ihs_osd osd;     /* 0x0200 */
        u16 reserved_5[761];    /* 0x020e */
-       u16 videomem;           /* 0x0800 */
+       u16 videomem[31736];    /* 0x0800 */
 };
 #endif