rockchip/rk3399: Change PD_CTR_LOOP to 10000

This brings ATF into line with the kernel on the timeout for power
domains turning on. We could actually timeout (when we shouldn't) on
resume when turning power domains on. The guaranteed maximum delay is
now 10ms.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
index 5c0ab4d71c67dd9db4748767fafcf48df395a8d2..0265dde4a6814f671fcb9bb3ce4a9c3bd8087553 100644 (file)
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
@@ -53,7 +53,7 @@ enum pmu_core_pwrst_shift {
 #define TSADC_INT_PIN          38
 #define CORES_PM_DISABLE       0x0
 
-#define PD_CTR_LOOP            500
+#define PD_CTR_LOOP            10000
 #define CHK_CPU_LOOP           500
 #define MAX_WAIT_COUNT         1000