--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
-@@ -239,6 +239,11 @@ config PHY_XGENE
+@@ -239,6 +239,11 @@
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
depends on RESET_CONTROLLER
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
-@@ -31,3 +31,4 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) +=
+@@ -31,3 +31,4 @@
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
-@@ -0,0 +1,177 @@
+@@ -0,0 +1,175 @@
+/*
+ * Allwinner ralink USB phy driver
+ *
+ struct phy_provider *phy_provider;
+ const struct of_device_id *match;
+
-+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
+ phy_clk = (int) match->data;
+
+ }
+
+ phy_provider = devm_of_phy_provider_register(dev, ralink_usb_phy_xlate);
-+printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
--- /dev/null
+From f5d9bea58b576b50cdc0d7a607646b0849ff79c4 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Mon, 25 May 2015 16:51:34 +0200
+Subject: [PATCH] MIPS: ralink: fix clearing the illegal access interrupt
+
+Due to a typo the illegal access interrupt is never cleared in by
+the interupt handler, causing an effective deadlock on the first
+illegal access.
+
+This was broken since the code was introduced in 5433acd81e87 ("MIPS:
+ralink: add illegal access driver"), but only exposed when the Kconfig
+symbol was added, thus enabling the code.
+
+Cc: <stable@vger.kernel.org> [3.18+]
+Fixes: a7b7aad383c ("MIPS: ralink: add missing symbol for RALINK_ILL_ACC")
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/ralink/ill_acc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/ralink/ill_acc.c
++++ b/arch/mips/ralink/ill_acc.c
+@@ -41,7 +41,7 @@ static irqreturn_t ill_acc_irq_handler(i
+ addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
+ type & ILL_ACC_LEN_M);
+
+- rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
++ rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
+
+ return IRQ_HANDLED;
+ }
--- /dev/null
+--- a/arch/mips/ralink/cevt-rt3352.c
++++ b/arch/mips/ralink/cevt-rt3352.c
+@@ -53,8 +53,7 @@ static int systick_next_event(unsigned l
+
+ sdev = container_of(evt, struct systick_device, dev);
+ count = ioread32(sdev->membase + SYSTICK_COUNT);
+- count = (count + delta) % SYSTICK_FREQ;
+- iowrite32(count, sdev->membase + SYSTICK_COMPARE);
++ iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
+
+ return 0;
+ }
--- /dev/null
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -13,9 +13,9 @@ config CLKEVT_RT3352
+ select CEVT_SYSTICK_QUIRK
+
+ config RALINK_ILL_ACC
+- bool
++ bool "illegal access irq"
+ depends on SOC_RT305X
+- default y
++ default n
+
+ config IRQ_INTC
+ bool
--- /dev/null
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -513,9 +513,6 @@ void prom_soc_init(struct ralink_soc_inf
+ ralink_soc = MT762X_SOC_MT7620N;
+ name = "MT7620N";
+ soc_info->compatible = "ralink,mt7620n-soc";
+-#ifdef CONFIG_PCI
+- panic("mt7620n is only supported for non pci kernels");
+-#endif
+ }
+ } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
+ ralink_soc = MT762X_SOC_MT7628AN;
--- /dev/null
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -98,7 +98,6 @@ static int __init mips_reboot_setup(void
+ {
+ _machine_restart = ralink_restart;
+ _machine_halt = ralink_halt;
+- pm_power_off = ralink_halt;
+
+ return 0;
+ }
--- /dev/null
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -11,6 +11,7 @@
+ #include <linux/pm.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
++#include <linux/delay.h>
+ #include <linux/reset-controller.h>
+
+ #include <asm/reboot.h>
+@@ -18,8 +19,10 @@
+ #include <asm/mach-ralink/ralink_regs.h>
+
+ /* Reset Control */
+-#define SYSC_REG_RESET_CTRL 0x034
+-#define RSTCTL_RESET_SYSTEM BIT(0)
++#define SYSC_REG_RESET_CTRL 0x034
++
++#define RSTCTL_RESET_PCI BIT(26)
++#define RSTCTL_RESET_SYSTEM BIT(0)
+
+ static int ralink_assert_device(struct reset_controller_dev *rcdev,
+ unsigned long id)
+@@ -83,6 +86,11 @@ void ralink_rst_init(void)
+
+ static void ralink_restart(char *command)
+ {
++ if (IS_ENABLED(CONFIG_PCI)) {
++ rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
++ mdelay(50);
++ }
++
+ local_irq_disable();
+ rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
+ unreachable();
--- /dev/null
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
+@@ -0,0 +1,65 @@
++/*
++ * Ralink MT7621 specific CPU feature overrides
++ *
++ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
++ *
++ * This file was derived from: include/asm-mips/cpu-features.h
++ * Copyright (C) 2003, 2004 Ralf Baechle
++ * Copyright (C) 2004 Maciej W. Rozycki
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ */
++#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
++#define _MT7621_CPU_FEATURE_OVERRIDES_H
++
++#define cpu_has_tlb 1
++#define cpu_has_4kex 1
++#define cpu_has_3k_cache 0
++#define cpu_has_4k_cache 1
++#define cpu_has_tx39_cache 0
++#define cpu_has_sb1_cache 0
++#define cpu_has_fpu 0
++#define cpu_has_32fpr 0
++#define cpu_has_counter 1
++#define cpu_has_watch 1
++#define cpu_has_divec 1
++
++#define cpu_has_prefetch 1
++#define cpu_has_ejtag 1
++#define cpu_has_llsc 1
++
++#define cpu_has_mips16 1
++#define cpu_has_mdmx 0
++#define cpu_has_mips3d 0
++#define cpu_has_smartmips 0
++
++#define cpu_has_mips32r1 1
++#define cpu_has_mips32r2 1
++#define cpu_has_mips64r1 0
++#define cpu_has_mips64r2 0
++
++#define cpu_has_dsp 1
++#define cpu_has_dsp2 0
++#define cpu_has_mipsmt 1
++
++#define cpu_has_64bits 0
++#define cpu_has_64bit_zero_reg 0
++#define cpu_has_64bit_gp_regs 0
++#define cpu_has_64bit_addresses 0
++
++#define cpu_dcache_line_size() 32
++#define cpu_icache_line_size() 32
++
++#define cpu_has_dc_aliases 0
++#define cpu_has_vtag_icache 0
++
++#define cpu_has_rixi 0
++#define cpu_has_tlbinv 0
++#define cpu_has_userlocal 1
++
++#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -51,6 +51,7 @@ choice
+ select SYS_SUPPORTS_MULTITHREADING
+ select SYS_SUPPORTS_SMP
+ select SYS_SUPPORTS_MIPS_CMP
++ select SYS_SUPPORTS_HIGHMEM
+ select IRQ_GIC
+ select HW_HAS_PCI
+
--- /dev/null
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -3,7 +3,7 @@
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ * Copyright (C) 2008-2014 Imre Kaloz <kaloz@openwrt.org>
+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ */
+@@ -66,6 +66,17 @@ static int __init early_init_dt_find_mem
+ return 0;
+ }
+
++static int chosen_dtb;
++
++static int __init early_init_dt_find_chosen(unsigned long node, const char *uname,
++ int depth, void *data)
++{
++ if (depth == 1 && !strcmp(uname, "chosen"))
++ chosen_dtb = 1;
++
++ return 0;
++}
++
+ extern struct boot_param_header __image_dtb;
+
+ void __init plat_mem_setup(void)
+@@ -78,7 +89,9 @@ void __init plat_mem_setup(void)
+ */
+ __dt_setup_arch(&__image_dtb);
+
+- strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
++ of_scan_flat_dt(early_init_dt_find_chosen, NULL);
++ if (chosen_dtb)
++ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
+
+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
+ if (memory_dtb)
--- /dev/null
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -714,6 +714,10 @@ config I2C_RALINK
+ tristate "Ralink I2C Controller"
+ select OF_I2C
+
++config I2C_MT7621
++ tristate "MT7621 I2C Controller"
++ select OF_I2C
++
+ config HAVE_S3C2410_I2C
+ bool
+ help
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -67,6 +67,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
+ obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
+ obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
+ obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
++obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
+ obj-$(CONFIG_I2C_QUP) += i2c-qup.o
+ obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
+ obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-mt7621.c
+@@ -0,0 +1,303 @@
++/*
++ * drivers/i2c/busses/i2c-mt7621.c
++ *
++ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
++ *
++ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
++ * (C) 2014 Sittisak <sittisaks@hotmail.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/reset.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <linux/io.h>
++#include <linux/err.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define REG_CONFIG_REG 0x00
++#define REG_CLKDIV_REG 0x04
++#define REG_DEVADDR_REG 0x08
++#define REG_ADDR_REG 0x0C
++#define REG_DATAOUT_REG 0x10
++#define REG_DATAIN_REG 0x14
++#define REG_STATUS_REG 0x18
++#define REG_STARTXFR_REG 0x1C
++#define REG_BYTECNT_REG 0x20
++#define REG_SM0_IS_AUTOMODE 0x28
++#define REG_SM0CTL0 0x40
++
++
++#define I2C_STARTERR 0x10
++#define I2C_ACKERR 0x08
++#define I2C_DATARDY 0x04
++#define I2C_SDOEMPTY 0x02
++#define I2C_BUSY 0x01
++
++/* I2C_CFG register bit field */
++#define I2C_CFG_ADDRLEN_8 (7<<5) /* 8 bits */
++#define I2C_CFG_DEVADLEN_7 (6<<2)
++#define I2C_CFG_ADDRDIS BIT(1)
++#define I2C_CFG_DEVADDIS BIT(0)
++
++#define I2C_CFG_DEFAULT (I2C_CFG_ADDRLEN_8 | \
++ I2C_CFG_DEVADLEN_7 | \
++ I2C_CFG_ADDRDIS)
++
++#define I2C_RETRY 0x1000
++
++#define CLKDIV_VALUE 333
++#define i2c_busy_loop (CLKDIV_VALUE*30)
++
++#define READ_CMD 0x01
++#define WRITE_CMD 0x00
++#define READ_BLOCK 16
++
++#define SM0_ODRAIN BIT(31)
++#define SM0_VSYNC_MODE BIT(28)
++#define SM0_CLK_DIV (CLKDIV_VALUE << 16)
++#define SM0_WAIT_LEVEL BIT(6)
++#define SM0_EN BIT(1)
++
++#define SM0_CFG_DEFUALT (SM0_ODRAIN | SM0_VSYNC_MODE | \
++ SM0_CLK_DIV | SM0_WAIT_LEVEL | \
++ SM0_EN)
++/***********************************************************/
++
++static void __iomem *membase;
++static struct i2c_adapter *adapter;
++
++static void rt_i2c_w32(u32 val, unsigned reg)
++{
++ iowrite32(val, membase + reg);
++}
++
++static u32 rt_i2c_r32(unsigned reg)
++{
++ return ioread32(membase + reg);
++}
++
++static void mt7621_i2c_reset(struct i2c_adapter *a)
++{
++ device_reset(a->dev.parent);
++}
++static void mt7621_i2c_enable(struct i2c_msg *msg)
++{
++ rt_i2c_w32(msg->addr,REG_DEVADDR_REG);
++ rt_i2c_w32(0,REG_ADDR_REG);
++}
++
++static void i2c_master_init(struct i2c_adapter *a)
++{
++ mt7621_i2c_reset(a);
++ rt_i2c_w32(I2C_CFG_DEFAULT,REG_CONFIG_REG);
++ rt_i2c_w32(SM0_CFG_DEFUALT,REG_SM0CTL0);
++ rt_i2c_w32(1,REG_SM0_IS_AUTOMODE);//auto mode
++}
++
++
++static inline int rt_i2c_wait_rx_done(void)
++{
++ int i=0;
++ while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY)) && (i<i2c_busy_loop))
++ i++;
++ if(i>=i2c_busy_loop){
++ pr_err("err,wait for idle timeout");
++ return -ETIMEDOUT;
++ }
++ return 0;
++}
++
++static inline int rt_i2c_wait_idle(void)
++{
++ int i=0;
++ while((rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY) && (i<i2c_busy_loop))
++ i++;
++ if(i>=i2c_busy_loop){
++ pr_err("err,wait for idle timeout");
++ return -ETIMEDOUT;
++ }
++ return 0;
++}
++
++static inline int rt_i2c_wait_tx_done(void)
++{
++ int i=0;
++ while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY)) && (i<i2c_busy_loop))
++ i++;
++ if(i>=i2c_busy_loop){
++ pr_err("err,wait for idle timeout");
++ return -ETIMEDOUT;
++ }
++ return 0;
++}
++
++static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
++{
++ int i = 0, j = 0, pos = 0;
++ int nblock = msg->len / READ_BLOCK;
++ int rem = msg->len % READ_BLOCK;
++
++ if (msg->flags & I2C_M_TEN) {
++ printk("10 bits addr not supported\n");
++ return -EINVAL;
++ }
++
++ if (msg->flags & I2C_M_RD) {
++ for (i = 0; i < nblock; i++) {
++ if (rt_i2c_wait_idle())
++ goto err_timeout;
++ rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
++ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
++ for (j = 0; j < READ_BLOCK; j++) {
++ if (rt_i2c_wait_rx_done())
++ goto err_timeout;
++ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
++ }
++ }
++
++ if (rt_i2c_wait_idle())
++ goto err_timeout;
++ rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
++ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
++
++ for (i = 0; i < rem; i++) {
++ if (rt_i2c_wait_rx_done())
++ goto err_timeout;
++ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
++ }
++ } else {
++ if (rt_i2c_wait_idle())
++ goto err_timeout;
++ rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
++ for (i = 0; i < msg->len; i++) {
++ rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
++ if(i == 0)
++ rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
++
++ if (rt_i2c_wait_tx_done())
++ goto err_timeout;
++ }
++ }
++
++ return 0;
++err_timeout:
++ return -ETIMEDOUT;
++}
++
++static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
++{
++ int i = 0;
++ int ret = 0;
++ i2c_master_init(a);
++ mt7621_i2c_enable(m);
++
++ for (i = 0; i != n && ret==0; i++) {
++ ret = rt_i2c_handle_msg(a, &m[i]);
++ if (ret)
++ return ret;
++ }
++ return i;
++}
++
++static u32 rt_i2c_func(struct i2c_adapter *a)
++{
++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++static const struct i2c_algorithm rt_i2c_algo = {
++ .master_xfer = rt_i2c_master_xfer,
++ .functionality = rt_i2c_func,
++};
++
++static int rt_i2c_probe(struct platform_device *pdev)
++{
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ int ret;
++
++ adapter = devm_kzalloc(&pdev->dev,sizeof(struct i2c_adapter), GFP_KERNEL);
++ if (!adapter) {
++ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
++ return -ENOMEM;
++ }
++ membase = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(membase))
++ return PTR_ERR(membase);
++
++ strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
++
++ adapter->owner = THIS_MODULE;
++ adapter->nr = pdev->id;
++ adapter->timeout = HZ;
++ adapter->algo = &rt_i2c_algo;
++ adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
++ adapter->dev.parent = &pdev->dev;
++ adapter->dev.of_node = pdev->dev.of_node;
++
++ platform_set_drvdata(pdev, adapter);
++
++ ret = i2c_add_numbered_adapter(adapter);
++ if (ret)
++ return ret;
++
++ dev_info(&pdev->dev,"loaded");
++
++ return 0;
++}
++
++static int rt_i2c_remove(struct platform_device *pdev)
++{
++ platform_set_drvdata(pdev, NULL);
++ return 0;
++}
++
++static const struct of_device_id i2c_rt_dt_ids[] = {
++ { .compatible = "ralink,i2c-mt7621", },
++ { /* sentinel */ }
++};
++
++MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
++
++static struct platform_driver rt_i2c_driver = {
++ .probe = rt_i2c_probe,
++ .remove = rt_i2c_remove,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "i2c-mt7621",
++ .of_match_table = i2c_rt_dt_ids,
++ },
++};
++
++static int __init i2c_rt_init (void)
++{
++ return platform_driver_register(&rt_i2c_driver);
++}
++
++static void __exit i2c_rt_exit (void)
++{
++ platform_driver_unregister(&rt_i2c_driver);
++}
++module_init (i2c_rt_init);
++module_exit (i2c_rt_exit);
++
++MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
++MODULE_DESCRIPTION("MT7621 I2c host driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:MT7621-I2C");
+++ /dev/null
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -3,7 +3,7 @@
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
-- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2008-2014 Imre Kaloz <kaloz@openwrt.org>
- * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
- * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
- */
-@@ -66,6 +66,17 @@ static int __init early_init_dt_find_mem
- return 0;
- }
-
-+static int chosen_dtb;
-+
-+static int __init early_init_dt_find_chosen(unsigned long node, const char *uname,
-+ int depth, void *data)
-+{
-+ if (depth == 1 && !strcmp(uname, "chosen"))
-+ chosen_dtb = 1;
-+
-+ return 0;
-+}
-+
- extern struct boot_param_header __image_dtb;
-
- void __init plat_mem_setup(void)
-@@ -78,7 +89,9 @@ void __init plat_mem_setup(void)
- */
- __dt_setup_arch(&__image_dtb);
-
-- strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
-+ of_scan_flat_dt(early_init_dt_find_chosen, NULL);
-+ if (chosen_dtb)
-+ strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
-
- of_scan_flat_dt(early_init_dt_find_memory, NULL);
- if (memory_dtb)
+++ /dev/null
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -714,6 +714,10 @@ config I2C_RALINK
- tristate "Ralink I2C Controller"
- select OF_I2C
-
-+config I2C_MT7621
-+ tristate "MT7621 I2C Controller"
-+ select OF_I2C
-+
- config HAVE_S3C2410_I2C
- bool
- help
---- a/drivers/i2c/busses/Makefile
-+++ b/drivers/i2c/busses/Makefile
-@@ -67,6 +67,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
- obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
- obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
- obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
-+obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
- obj-$(CONFIG_I2C_QUP) += i2c-qup.o
- obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
- obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
---- /dev/null
-+++ b/drivers/i2c/busses/i2c-mt7621.c
-@@ -0,0 +1,303 @@
-+/*
-+ * drivers/i2c/busses/i2c-mt7621.c
-+ *
-+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
-+ *
-+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
-+ * (C) 2014 Sittisak <sittisaks@hotmail.com>
-+ *
-+ * This software is licensed under the terms of the GNU General Public
-+ * License version 2, as published by the Free Software Foundation, and
-+ * may be copied, distributed, and modified under those terms.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/reset.h>
-+#include <linux/delay.h>
-+#include <linux/slab.h>
-+#include <linux/init.h>
-+#include <linux/errno.h>
-+#include <linux/platform_device.h>
-+#include <linux/i2c.h>
-+#include <linux/io.h>
-+#include <linux/err.h>
-+
-+#include <asm/mach-ralink/ralink_regs.h>
-+
-+#define REG_CONFIG_REG 0x00
-+#define REG_CLKDIV_REG 0x04
-+#define REG_DEVADDR_REG 0x08
-+#define REG_ADDR_REG 0x0C
-+#define REG_DATAOUT_REG 0x10
-+#define REG_DATAIN_REG 0x14
-+#define REG_STATUS_REG 0x18
-+#define REG_STARTXFR_REG 0x1C
-+#define REG_BYTECNT_REG 0x20
-+#define REG_SM0_IS_AUTOMODE 0x28
-+#define REG_SM0CTL0 0x40
-+
-+
-+#define I2C_STARTERR 0x10
-+#define I2C_ACKERR 0x08
-+#define I2C_DATARDY 0x04
-+#define I2C_SDOEMPTY 0x02
-+#define I2C_BUSY 0x01
-+
-+/* I2C_CFG register bit field */
-+#define I2C_CFG_ADDRLEN_8 (7<<5) /* 8 bits */
-+#define I2C_CFG_DEVADLEN_7 (6<<2)
-+#define I2C_CFG_ADDRDIS BIT(1)
-+#define I2C_CFG_DEVADDIS BIT(0)
-+
-+#define I2C_CFG_DEFAULT (I2C_CFG_ADDRLEN_8 | \
-+ I2C_CFG_DEVADLEN_7 | \
-+ I2C_CFG_ADDRDIS)
-+
-+#define I2C_RETRY 0x1000
-+
-+#define CLKDIV_VALUE 333
-+#define i2c_busy_loop (CLKDIV_VALUE*30)
-+
-+#define READ_CMD 0x01
-+#define WRITE_CMD 0x00
-+#define READ_BLOCK 16
-+
-+#define SM0_ODRAIN BIT(31)
-+#define SM0_VSYNC_MODE BIT(28)
-+#define SM0_CLK_DIV (CLKDIV_VALUE << 16)
-+#define SM0_WAIT_LEVEL BIT(6)
-+#define SM0_EN BIT(1)
-+
-+#define SM0_CFG_DEFUALT (SM0_ODRAIN | SM0_VSYNC_MODE | \
-+ SM0_CLK_DIV | SM0_WAIT_LEVEL | \
-+ SM0_EN)
-+/***********************************************************/
-+
-+static void __iomem *membase;
-+static struct i2c_adapter *adapter;
-+
-+static void rt_i2c_w32(u32 val, unsigned reg)
-+{
-+ iowrite32(val, membase + reg);
-+}
-+
-+static u32 rt_i2c_r32(unsigned reg)
-+{
-+ return ioread32(membase + reg);
-+}
-+
-+static void mt7621_i2c_reset(struct i2c_adapter *a)
-+{
-+ device_reset(a->dev.parent);
-+}
-+static void mt7621_i2c_enable(struct i2c_msg *msg)
-+{
-+ rt_i2c_w32(msg->addr,REG_DEVADDR_REG);
-+ rt_i2c_w32(0,REG_ADDR_REG);
-+}
-+
-+static void i2c_master_init(struct i2c_adapter *a)
-+{
-+ mt7621_i2c_reset(a);
-+ rt_i2c_w32(I2C_CFG_DEFAULT,REG_CONFIG_REG);
-+ rt_i2c_w32(SM0_CFG_DEFUALT,REG_SM0CTL0);
-+ rt_i2c_w32(1,REG_SM0_IS_AUTOMODE);//auto mode
-+}
-+
-+
-+static inline int rt_i2c_wait_rx_done(void)
-+{
-+ int i=0;
-+ while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY)) && (i<i2c_busy_loop))
-+ i++;
-+ if(i>=i2c_busy_loop){
-+ pr_err("err,wait for idle timeout");
-+ return -ETIMEDOUT;
-+ }
-+ return 0;
-+}
-+
-+static inline int rt_i2c_wait_idle(void)
-+{
-+ int i=0;
-+ while((rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY) && (i<i2c_busy_loop))
-+ i++;
-+ if(i>=i2c_busy_loop){
-+ pr_err("err,wait for idle timeout");
-+ return -ETIMEDOUT;
-+ }
-+ return 0;
-+}
-+
-+static inline int rt_i2c_wait_tx_done(void)
-+{
-+ int i=0;
-+ while((!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY)) && (i<i2c_busy_loop))
-+ i++;
-+ if(i>=i2c_busy_loop){
-+ pr_err("err,wait for idle timeout");
-+ return -ETIMEDOUT;
-+ }
-+ return 0;
-+}
-+
-+static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
-+{
-+ int i = 0, j = 0, pos = 0;
-+ int nblock = msg->len / READ_BLOCK;
-+ int rem = msg->len % READ_BLOCK;
-+
-+ if (msg->flags & I2C_M_TEN) {
-+ printk("10 bits addr not supported\n");
-+ return -EINVAL;
-+ }
-+
-+ if (msg->flags & I2C_M_RD) {
-+ for (i = 0; i < nblock; i++) {
-+ if (rt_i2c_wait_idle())
-+ goto err_timeout;
-+ rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
-+ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
-+ for (j = 0; j < READ_BLOCK; j++) {
-+ if (rt_i2c_wait_rx_done())
-+ goto err_timeout;
-+ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
-+ }
-+ }
-+
-+ if (rt_i2c_wait_idle())
-+ goto err_timeout;
-+ rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
-+ rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
-+
-+ for (i = 0; i < rem; i++) {
-+ if (rt_i2c_wait_rx_done())
-+ goto err_timeout;
-+ msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
-+ }
-+ } else {
-+ if (rt_i2c_wait_idle())
-+ goto err_timeout;
-+ rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
-+ for (i = 0; i < msg->len; i++) {
-+ rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
-+ if(i == 0)
-+ rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
-+
-+ if (rt_i2c_wait_tx_done())
-+ goto err_timeout;
-+ }
-+ }
-+
-+ return 0;
-+err_timeout:
-+ return -ETIMEDOUT;
-+}
-+
-+static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
-+{
-+ int i = 0;
-+ int ret = 0;
-+ i2c_master_init(a);
-+ mt7621_i2c_enable(m);
-+
-+ for (i = 0; i != n && ret==0; i++) {
-+ ret = rt_i2c_handle_msg(a, &m[i]);
-+ if (ret)
-+ return ret;
-+ }
-+ return i;
-+}
-+
-+static u32 rt_i2c_func(struct i2c_adapter *a)
-+{
-+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-+}
-+
-+static const struct i2c_algorithm rt_i2c_algo = {
-+ .master_xfer = rt_i2c_master_xfer,
-+ .functionality = rt_i2c_func,
-+};
-+
-+static int rt_i2c_probe(struct platform_device *pdev)
-+{
-+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ int ret;
-+
-+ adapter = devm_kzalloc(&pdev->dev,sizeof(struct i2c_adapter), GFP_KERNEL);
-+ if (!adapter) {
-+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
-+ return -ENOMEM;
-+ }
-+ membase = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(membase))
-+ return PTR_ERR(membase);
-+
-+ strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
-+
-+ adapter->owner = THIS_MODULE;
-+ adapter->nr = pdev->id;
-+ adapter->timeout = HZ;
-+ adapter->algo = &rt_i2c_algo;
-+ adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
-+ adapter->dev.parent = &pdev->dev;
-+ adapter->dev.of_node = pdev->dev.of_node;
-+
-+ platform_set_drvdata(pdev, adapter);
-+
-+ ret = i2c_add_numbered_adapter(adapter);
-+ if (ret)
-+ return ret;
-+
-+ dev_info(&pdev->dev,"loaded");
-+
-+ return 0;
-+}
-+
-+static int rt_i2c_remove(struct platform_device *pdev)
-+{
-+ platform_set_drvdata(pdev, NULL);
-+ return 0;
-+}
-+
-+static const struct of_device_id i2c_rt_dt_ids[] = {
-+ { .compatible = "ralink,i2c-mt7621", },
-+ { /* sentinel */ }
-+};
-+
-+MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
-+
-+static struct platform_driver rt_i2c_driver = {
-+ .probe = rt_i2c_probe,
-+ .remove = rt_i2c_remove,
-+ .driver = {
-+ .owner = THIS_MODULE,
-+ .name = "i2c-mt7621",
-+ .of_match_table = i2c_rt_dt_ids,
-+ },
-+};
-+
-+static int __init i2c_rt_init (void)
-+{
-+ return platform_driver_register(&rt_i2c_driver);
-+}
-+
-+static void __exit i2c_rt_exit (void)
-+{
-+ platform_driver_unregister(&rt_i2c_driver);
-+}
-+module_init (i2c_rt_init);
-+module_exit (i2c_rt_exit);
-+
-+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
-+MODULE_DESCRIPTION("MT7621 I2c host driver");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:MT7621-I2C");
+++ /dev/null
-From f5d9bea58b576b50cdc0d7a607646b0849ff79c4 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Mon, 25 May 2015 16:51:34 +0200
-Subject: [PATCH] MIPS: ralink: fix clearing the illegal access interrupt
-
-Due to a typo the illegal access interrupt is never cleared in by
-the interupt handler, causing an effective deadlock on the first
-illegal access.
-
-This was broken since the code was introduced in 5433acd81e87 ("MIPS:
-ralink: add illegal access driver"), but only exposed when the Kconfig
-symbol was added, thus enabling the code.
-
-Cc: <stable@vger.kernel.org> [3.18+]
-Fixes: a7b7aad383c ("MIPS: ralink: add missing symbol for RALINK_ILL_ACC")
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/ralink/ill_acc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/ralink/ill_acc.c
-+++ b/arch/mips/ralink/ill_acc.c
-@@ -41,7 +41,7 @@ static irqreturn_t ill_acc_irq_handler(i
- addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
- type & ILL_ACC_LEN_M);
-
-- rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
-+ rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
-
- return IRQ_HANDLED;
- }
+++ /dev/null
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ralink/mt7621/cpu-feature-overrides.h
-@@ -0,0 +1,65 @@
-+/*
-+ * Ralink MT7621 specific CPU feature overrides
-+ *
-+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * This file was derived from: include/asm-mips/cpu-features.h
-+ * Copyright (C) 2003, 2004 Ralf Baechle
-+ * Copyright (C) 2004 Maciej W. Rozycki
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ */
-+#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
-+#define _MT7621_CPU_FEATURE_OVERRIDES_H
-+
-+#define cpu_has_tlb 1
-+#define cpu_has_4kex 1
-+#define cpu_has_3k_cache 0
-+#define cpu_has_4k_cache 1
-+#define cpu_has_tx39_cache 0
-+#define cpu_has_sb1_cache 0
-+#define cpu_has_fpu 0
-+#define cpu_has_32fpr 0
-+#define cpu_has_counter 1
-+#define cpu_has_watch 1
-+#define cpu_has_divec 1
-+
-+#define cpu_has_prefetch 1
-+#define cpu_has_ejtag 1
-+#define cpu_has_llsc 1
-+
-+#define cpu_has_mips16 1
-+#define cpu_has_mdmx 0
-+#define cpu_has_mips3d 0
-+#define cpu_has_smartmips 0
-+
-+#define cpu_has_mips32r1 1
-+#define cpu_has_mips32r2 1
-+#define cpu_has_mips64r1 0
-+#define cpu_has_mips64r2 0
-+
-+#define cpu_has_dsp 1
-+#define cpu_has_dsp2 0
-+#define cpu_has_mipsmt 1
-+
-+#define cpu_has_64bits 0
-+#define cpu_has_64bit_zero_reg 0
-+#define cpu_has_64bit_gp_regs 0
-+#define cpu_has_64bit_addresses 0
-+
-+#define cpu_dcache_line_size() 32
-+#define cpu_icache_line_size() 32
-+
-+#define cpu_has_dc_aliases 0
-+#define cpu_has_vtag_icache 0
-+
-+#define cpu_has_rixi 0
-+#define cpu_has_tlbinv 0
-+#define cpu_has_userlocal 1
-+
-+#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */
+++ /dev/null
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -51,6 +51,7 @@ choice
- select SYS_SUPPORTS_MULTITHREADING
- select SYS_SUPPORTS_SMP
- select SYS_SUPPORTS_MIPS_CMP
-+ select SYS_SUPPORTS_HIGHMEM
- select IRQ_GIC
- select HW_HAS_PCI
-
+++ /dev/null
---- a/arch/mips/ralink/cevt-rt3352.c
-+++ b/arch/mips/ralink/cevt-rt3352.c
-@@ -53,8 +53,7 @@ static int systick_next_event(unsigned l
-
- sdev = container_of(evt, struct systick_device, dev);
- count = ioread32(sdev->membase + SYSTICK_COUNT);
-- count = (count + delta) % SYSTICK_FREQ;
-- iowrite32(count, sdev->membase + SYSTICK_COMPARE);
-+ iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
-
- return 0;
- }
+++ /dev/null
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -13,9 +13,9 @@ config CLKEVT_RT3352
- select CEVT_SYSTICK_QUIRK
-
- config RALINK_ILL_ACC
-- bool
-+ bool "illegal access irq"
- depends on SOC_RT305X
-- default y
-+ default n
-
- config IRQ_INTC
- bool
+++ /dev/null
---- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -98,7 +98,6 @@ static int __init mips_reboot_setup(void
- {
- _machine_restart = ralink_restart;
- _machine_halt = ralink_halt;
-- pm_power_off = ralink_halt;
-
- return 0;
- }
+++ /dev/null
---- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -513,9 +513,6 @@ void prom_soc_init(struct ralink_soc_inf
- ralink_soc = MT762X_SOC_MT7620N;
- name = "MT7620N";
- soc_info->compatible = "ralink,mt7620n-soc";
--#ifdef CONFIG_PCI
-- panic("mt7620n is only supported for non pci kernels");
--#endif
- }
- } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
- ralink_soc = MT762X_SOC_MT7628AN;
+++ /dev/null
---- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -11,6 +11,7 @@
- #include <linux/pm.h>
- #include <linux/io.h>
- #include <linux/of.h>
-+#include <linux/delay.h>
- #include <linux/reset-controller.h>
-
- #include <asm/reboot.h>
-@@ -18,8 +19,10 @@
- #include <asm/mach-ralink/ralink_regs.h>
-
- /* Reset Control */
--#define SYSC_REG_RESET_CTRL 0x034
--#define RSTCTL_RESET_SYSTEM BIT(0)
-+#define SYSC_REG_RESET_CTRL 0x034
-+
-+#define RSTCTL_RESET_PCI BIT(26)
-+#define RSTCTL_RESET_SYSTEM BIT(0)
-
- static int ralink_assert_device(struct reset_controller_dev *rcdev,
- unsigned long id)
-@@ -83,6 +86,11 @@ void ralink_rst_init(void)
-
- static void ralink_restart(char *command)
- {
-+ if (IS_ENABLED(CONFIG_PCI)) {
-+ rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL);
-+ mdelay(50);
-+ }
-+
- local_irq_disable();
- rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL);
- unreachable();
projects / openwrt / staging / stintel.git / commitdiff