break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240;
local_irq_save(flags);
t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240;
local_irq_save(flags);
t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
local_irq_save(flags);
t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
local_irq_restore(flags);
/* WAR for HW bug. Here it adjusts the duration between two SOFS */
ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3);
- ar71xx_ohci_device.resource = ar7240_ohci_resources;
- ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources);
-
- platform_device_register(&ar71xx_ohci_device);
+ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) {
+ ar71xx_ehci_data.is_ar91xx = 1;
+ ar71xx_ehci_device.resource = ar7240_ohci_resources;
+ ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources);
+ platform_device_register(&ar71xx_ehci_device);
+ } else {
+ ar71xx_ohci_device.resource = ar7240_ohci_resources;
+ ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources);
+ platform_device_register(&ar71xx_ohci_device);
+ }
}
static void __init ar91xx_usb_setup(void)
{
switch (ar71xx_soc) {
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
ar7240_usb_setup();
break;
void __init ar71xx_add_device_mdio(u32 phy_mask)
{
- if (ar71xx_soc == AR71XX_SOC_AR7240)
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
ar71xx_mdio_data.is_ar7240 = 1;
+ break;
+ default:
+ break;
+ }
ar71xx_mdio_data.phy_mask = phy_mask;
break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
pll_10 = AR724X_PLL_VAL_10;
pll_100 = AR724X_PLL_VAL_100;
pll_1000 = AR724X_PLL_VAL_1000;
break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
: ar724x_ddr_flush_ge0;
pdata->set_pll = id ? ar724x_set_pll_ge1
break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT;
break;
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
__raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
- if (ar71xx_soc == AR71XX_SOC_AR7240)
+ switch (ar71xx_soc) {
+ case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
- else
+ break;
+ default:
ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
+ break;
+ }
for (i = AR71XX_MISC_IRQ_BASE;
i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
ret = ar724x_pcibios_map_irq(dev, slot, pin);
break;
break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
ret = ar724x_pcibios_init();
break;
}
break;
- case REV_ID_MAJOR_AR724X:
+ case REV_ID_MAJOR_AR7240:
ar71xx_soc = AR71XX_SOC_AR7240;
chip = "7240";
rev = (id & AR724X_REV_ID_REVISION_MASK);
break;
+ case REV_ID_MAJOR_AR7241:
+ ar71xx_soc = AR71XX_SOC_AR7241;
+ chip = "7241";
+ rev = (id & AR724X_REV_ID_REVISION_MASK);
+ break;
+
+ case REV_ID_MAJOR_AR7242:
+ ar71xx_soc = AR71XX_SOC_AR7242;
+ chip = "7242";
+ rev = (id & AR724X_REV_ID_REVISION_MASK);
+ break;
+
case REV_ID_MAJOR_AR913X:
minor = id & AR91XX_REV_ID_MINOR_MASK;
rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
break;
case AR71XX_SOC_AR7240:
+ case AR71XX_SOC_AR7241:
+ case AR71XX_SOC_AR7242:
ar724x_detect_sys_frequency();
break;
AR71XX_SOC_AR7141,
AR71XX_SOC_AR7161,
AR71XX_SOC_AR7240,
+ AR71XX_SOC_AR7241,
+ AR71XX_SOC_AR7242,
AR71XX_SOC_AR9130,
AR71XX_SOC_AR9132
};
#define AR724X_RESET_PCIE_PHY BIT(7)
#define AR724X_RESET_PCIE BIT(6)
-#define REV_ID_MAJOR_MASK 0xf0
-#define REV_ID_MAJOR_AR71XX 0xa0
-#define REV_ID_MAJOR_AR913X 0xb0
-#define REV_ID_MAJOR_AR724X 0xc0
+#define REV_ID_MAJOR_MASK 0xfff0
+#define REV_ID_MAJOR_AR71XX 0x00a0
+#define REV_ID_MAJOR_AR913X 0x00b0
+#define REV_ID_MAJOR_AR7240 0x00c0
+#define REV_ID_MAJOR_AR7241 0x0100
+#define REV_ID_MAJOR_AR7242 0x1100
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
return -ENODEV;
}
+ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) {
+ t = __raw_readl(base + AR724X_PCI_REG_APP);
+ t |= BIT(16);
+ __raw_writel(t, base + AR724X_PCI_REG_APP);
+ }
+
return 0;
}