net: cavium: Register driver with PCI subsys IDs
authorPrakash Brahmajyosyula <bprakash@marvell.com>
Mon, 2 Mar 2020 09:59:02 +0000 (15:29 +0530)
committerDavid S. Miller <davem@davemloft.net>
Mon, 2 Mar 2020 19:13:58 +0000 (11:13 -0800)
Across Cavium's ThunderX and Marvell's OcteonTx2 silicons
the PTP timestamping block's PCI device ID and vendor ID
have remained same but the HW architecture has changed.

Hence added PCI subsystem IDs to the device table to avoid
this driver from being probed on OcteonTx2 silicons.

Signed-off-by: Prakash Brahmajyosyula <bprakash@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/cavium/common/cavium_ptp.c

index b821c9e1604cff9c9b6ea412615140f293d5ee68..81ff9ac73f9a38c0dcdd27ee8861dea489ba3483 100644 (file)
@@ -13,6 +13,9 @@
 #define DRV_NAME "cavium_ptp"
 
 #define PCI_DEVICE_ID_CAVIUM_PTP       0xA00C
+#define PCI_SUBSYS_DEVID_88XX_PTP      0xA10C
+#define PCI_SUBSYS_DEVID_81XX_PTP      0XA20C
+#define PCI_SUBSYS_DEVID_83XX_PTP      0xA30C
 #define PCI_DEVICE_ID_CAVIUM_RST       0xA00E
 
 #define PCI_PTP_BAR_NO 0
@@ -321,7 +324,12 @@ static void cavium_ptp_remove(struct pci_dev *pdev)
 }
 
 static const struct pci_device_id cavium_ptp_id_table[] = {
-       { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
+                       PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_88XX_PTP) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
+                       PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_81XX_PTP) },
+       { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
+                       PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_83XX_PTP) },
        { 0, }
 };