struct nouveau_pm_memtiming *boot,
struct nouveau_pm_memtiming *t)
{
+ u8 rver, rlen, *ramcfg = nouveau_perf_ramcfg(dev, freq, &rver, &rlen);
+
if (len < 15) {
t->drive_strength = boot->drive_strength;
t->odt = boot->odt;
/* CAS */
((nv_mem_cl_lut_gddr3[e->tCL] & 0x7) << 4) |
((nv_mem_cl_lut_gddr3[e->tCL] & 0x8) >> 2);
+
t->mr[1] = (boot->mr[1] & 0x100f40) | t->drive_strength |
(t->odt << 2) |
(nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4;
+ if (ramcfg && rver == 0x00) {
+ /* DLL enable/disable */
+ t->mr[1] &= ~0x00000040;
+ if (ramcfg[3] & 0x08)
+ t->mr[1] |= 0x00000040;
+ }
+
t->mr[2] = boot->mr[2];
NV_DEBUG(dev, "(%u) MR: %08x %08x %08x", t->id,
void nouveau_perf_init(struct drm_device *);
void nouveau_perf_fini(struct drm_device *);
u8 *nouveau_perf_timing(struct drm_device *, u32 freq, u8 *ver, u8 *len);
+u8 *nouveau_perf_ramcfg(struct drm_device *, u32 freq, u8 *ver, u8 *len);
/* nouveau_mem.c */
void nouveau_mem_timing_init(struct drm_device *);