level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
if (IS_ICELAKE(dev_priv)) {
- if (port == PORT_A || port == PORT_B)
+ if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port,
INTEL_OUTPUT_HDMI, &n_entries);
else
uint32_t pll_id;
pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
- if (port == PORT_A || port == PORT_B) {
+ if (intel_port_is_combophy(dev_priv, port)) {
if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
else
int n_entries;
if (IS_ICELAKE(dev_priv)) {
- if (port == PORT_A || port == PORT_B)
+ if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port, encoder->type,
&n_entries);
else
u32 level,
enum intel_output_type type)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
- if (port == PORT_A || port == PORT_B)
+ if (intel_port_is_combophy(dev_priv, port))
icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
else
icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
val = I915_READ(DPCLKA_CFGCR0_ICL);
WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
- if (port == PORT_A || port == PORT_B) {
+ if (intel_port_is_combophy(dev_priv, port)) {
val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
mutex_lock(&dev_priv->dpll_lock);
if (IS_ICELAKE(dev_priv)) {
- if (port >= PORT_C)
+ if (!intel_port_is_combophy(dev_priv, port))
I915_WRITE(DDI_CLK_SEL(port),
icl_pll_to_ddi_pll_sel(encoder, pll));
} else if (IS_CANNONLAKE(dev_priv)) {
enum port port = encoder->port;
if (IS_ICELAKE(dev_priv)) {
- if (port >= PORT_C)
+ if (!intel_port_is_combophy(dev_priv, port))
I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
} else if (IS_CANNONLAKE(dev_priv)) {
I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |