clk: qoriq: add ls1088a hwaccel clocks support

This patch is to add hwaccel clocks information for ls1088a.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Link: https://lkml.kernel.org/r/20191216100111.17122-1-yangbo.lu@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index bed140f7375f0ff88b047011c8a426f178b9b330..d5946f7486d6c21fd904b46ee9434f891a3c5dcb 100644 (file)
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -342,6 +342,32 @@ static const struct clockgen_muxinfo ls1046a_hwa2 = {
        },
 };
 
+static const struct clockgen_muxinfo ls1088a_hwa1 = {
+       {
+               {},
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
+               {},
+               { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+               { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+       },
+};
+
+static const struct clockgen_muxinfo ls1088a_hwa2 = {
+       {
+               {},
+               { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
+               { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
+               { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
+               { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
+               {},
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
+       },
+};
+
 static const struct clockgen_muxinfo ls1012a_cmux = {
        {
                [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
@@ -607,6 +633,9 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .cmux_groups = {
                        &clockgen2_cmux_cga12
                },
+               .hwaccel = {
+                       &ls1088a_hwa1, &ls1088a_hwa2
+               },
                .cmux_to_group = {
                        0, 0, -1
                },