MIPS: Probe guest MVH
authorJames Hogan <james.hogan@imgtec.com>
Tue, 14 Mar 2017 10:15:11 +0000 (10:15 +0000)
committerJames Hogan <james.hogan@imgtec.com>
Tue, 28 Mar 2017 13:49:15 +0000 (14:49 +0100)
Probe for availablility of M{T,F}HC0 instructions used with e.g. XPA in
the VZ guest context, and make it available via cpu_guest_has_mvh. This
will be helpful in properly emulating the MAAR registers in KVM for MIPS
VZ.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
arch/mips/include/asm/cpu-features.h
arch/mips/kernel/cpu-probe.c

index e898f441cc2227562ecae8fe5347c3c32a0781c2..494d38274142697b62c4ff3959c859bd1fc91d64 100644 (file)
 #ifndef cpu_guest_has_htw
 #define cpu_guest_has_htw      (cpu_data[0].guest.options & MIPS_CPU_HTW)
 #endif
+#ifndef cpu_guest_has_mvh
+#define cpu_guest_has_mvh      (cpu_data[0].guest.options & MIPS_CPU_MVH)
+#endif
 #ifndef cpu_guest_has_msa
 #define cpu_guest_has_msa      (cpu_data[0].guest.ases & MIPS_ASE_MSA)
 #endif
index 29dfdb64ad0b636705491fee8e3931484a30a8b0..c72a4cda389ce8cfb257a0299b8a5e22ac9132bf 100644 (file)
@@ -1057,7 +1057,7 @@ static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
        unsigned int config5, config5_dyn;
 
        probe_gc0_config_dyn(config5, config5, config5_dyn,
-                        MIPS_CONF_M | MIPS_CONF5_MRP);
+                        MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
 
        if (config5 & MIPS_CONF5_MRP)
                c->guest.options |= MIPS_CPU_MAAR;
@@ -1067,6 +1067,9 @@ static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
        if (config5 & MIPS_CONF5_LLB)
                c->guest.options |= MIPS_CPU_RW_LLB;
 
+       if (config5 & MIPS_CONF5_MVH)
+               c->guest.options |= MIPS_CPU_MVH;
+
        if (config5 & MIPS_CONF_M)
                c->guest.conf |= BIT(6);
        return config5 & MIPS_CONF_M;