dts: zynq: Add zynq spi controller nodes

This patch adds zynq spi controller nodes in zynq-7000.dtsi.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 2d076f194e06035946f528a639a62a45fa3a648f..f66f8dcaf8ddbfa872beeebd090c699781a8bd69 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -109,6 +109,30 @@
                        interrupts = <0 50 4>;
                };
 
+               spi0: spi@e0006000 {
+                       compatible = "xlnx,zynq-spi";
+                       reg = <0xe0006000 0x1000>;
+                       status = "disabled";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 26 4>;
+                       clocks = <&clkc 25>, <&clkc 34>;
+                       clock-names = "ref_clk", "pclk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               spi1: spi@e0007000 {
+                       compatible = "xlnx,zynq-spi";
+                       reg = <0xe0007000 0x1000>;
+                       status = "disabled";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 49 4>;
+                       clocks = <&clkc 26>, <&clkc 35>;
+                       clock-names = "ref_clk", "pclk";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                gem0: ethernet@e000b000 {
                        compatible = "cdns,gem";
                        reg = <0xe000b000 0x4000>;

diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt b/doc/device-tree-bindings/spi/spi-zynq.txt
new file mode 100644 (file)
index 0000000..a7c2757
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-zynq.txt
@@ -0,0 +1,27 @@
+Zynq SPI controller Device Tree Bindings
+----------------------------------------
+
+Required properties:
+- compatible           : Should be "xlnx,spi-zynq".
+- reg                  : Physical base address and size of SPI registers map.
+- status               : Status will be disabled in dtsi and enabled in required dts.
+- interrupt-parent     : Must be core interrupt controller.
+- interrupts           : Property with a value describing the interrupt
+                         number.
+- clocks               : Clock phandles (see clock bindings for details).
+- clock-names          : List of input clock names - "ref_clk", "pclk"
+                         (See clock bindings for details).
+
+Example:
+
+       spi@e0006000 {
+               compatible = "xlnx,zynq-spi";
+               reg = <0xe0006000 0x1000>;
+               status = "disabled";
+               interrupt-parent = <&intc>;
+               interrupts = <0 26 4>;
+               clocks = <&clkc 25>, <&clkc 34>;
+               clock-names = "ref_clk", "pclk";
+               #address-cells = <1>;
+               #size-cells = <0>;
+       } ;