i.MX6: define IOMUX_GPR3 register bitfields

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 8834c59dccefe40dbc4007dfbfa71ed73e74d22a..f9b08325eb4448d97abb26a8f2ac33d48f3acc63 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -200,6 +200,54 @@ struct src {
        u32     gpr10;
 };
 
+/* GPR3 bitfields */
+#define IOMUXC_GPR3_GPU_DBG_OFFSET             29
+#define IOMUXC_GPR3_GPU_DBG_MASK               (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET    28
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK      (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET    27
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK      (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK   (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK   (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_OFFSET           21
+#define IOMUXC_GPR3_OCRAM_CTL_MASK             (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET                17
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK          (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET    16
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK      (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET    15
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK      (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET    14
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK      (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET    13
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK      (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET    12
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK      (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET    11
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK      (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_OFFSET            10
+#define IOMUXC_GPR3_IPU_DIAG_MASK              (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0   0
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1   1
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0   2
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1   3
+
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET       8
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK         (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET       6
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK         (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET                4
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK          (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET                2
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK          (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+
+
 /* ECSPI registers */
 struct cspi_regs {
        u32 rxdata;