+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_d-link_dgs-1210_common.dtsi"
-#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
-
-/ {
- compatible = "d-link,dgs-1210-10mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc";
-
- model = "D-Link DGS-1210-10MP F";
-
- /* i2c for sfp port9 */
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-p9 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- };
-
- /* i2c for sfp port10 */
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-p10 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&leds {
- link_act {
- label = "green:link_act";
- gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
- };
-
- poe {
- label = "green:poe";
- gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
- };
-
- poe_max {
- label = "yellow:poe_max";
- gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
- };
-};
-
-&keys {
- mode {
- label = "mode";
- gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- port@24 {
- reg = <24>;
- label = "lan9";
- phy-handle = <&phy24>;
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp0>;
- };
-
- port@26 {
- reg = <26>;
- label = "lan10";
- phy-handle = <&phy26>;
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp1>;
- };
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "engenius,ews2910p", "realtek,rtl838x-soc";
- model = "EnGenius EWS2910P";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_fault;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x10000000>;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- led_mode {
- label = "led-mode";
- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
- };
-
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <0>;
-
- poe_enable {
- gpio-hog;
- gpios = <1 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "poe-enable";
- };
-
- sff_p9_gpios {
- gpio-hog;
- gpios = < 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>,
- < 11 GPIO_ACTIVE_HIGH>, /* los-gpio */
- < 12 GPIO_ACTIVE_LOW>; /* mod-def0-gpio */
- input;
- line-name = "sff-p9-gpios";
- };
- };
-
- gpio-export {
- compatible = "gpio-export";
-
- sff-p9-tx-disable {
- gpio-export,name = "sff-p9-tx-disable";
- gpio-export,output = <1>;
- gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: led-0 {
- label = "green:power";
- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- };
-
- led_lan_mode: led-1 {
- label = "green:lan-mode";
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- };
-
- led_fault: led-2 {
- label = "amber:fault";
- gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
- };
-
- led_poe_max: led-3 {
- label = "amber:poe-max";
- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
- };
- };
-
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- sfp1: sfp-p10 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x80000>;
- read-only;
- };
- partition@80000 {
- label = "u-boot-env";
- reg = <0x80000 0x10000>;
- read-only;
- };
- partition@90000 {
- label = "u-boot-env2";
- reg = <0x90000 0x10000>;
- };
- partition@a0000 {
- label = "rootfs_data";
- reg = <0xa0000 0xd60000>;
- };
- partition@e00000 {
- label = "jffs2-log";
- reg = <0xe00000 0x200000>;
- };
- partition@1000000 {
- compatible = "openwrt,uimage";
- label = "firmware";
- reg = <0x1000000 0x800000>;
- openwrt,ih-magic = <0x03802910>;
- };
- partition@1800000 {
- label = "firmware2";
- reg = <0x1800000 0x800000>;
- };
- };
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- SWITCH_SFP_PORT(24, 9, 1000base-x)
-
- port@26 {
- reg = <26>;
- label = "lan10";
- phy-mode = "1000base-x";
- phy-handle = <&phy26>;
- managed = "in-band-status";
- sfp = <&sfp1>;
- };
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
-
-&uart1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl8380_hpe_1920-8g.dtsi"
-
-/ {
- compatible = "hpe,1920-8g-poe-180w", "realtek,rtl838x-soc";
- model = "HPE 1920-8G-PoE+ 180W (JG922A)";
-};
-
-&uart1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl8380_hpe_1920-8g.dtsi"
-
-/ {
- compatible = "hpe,1920-8g-poe-65w", "realtek,rtl838x-soc";
- model = "HPE 1920-8G-PoE+ 65W (JG921A)";
-};
-
-&uart1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl8380_hpe_1920-8g.dtsi"
-
-/ {
- compatible = "hpe,1920-8g", "realtek,rtl838x-soc";
- model = "HPE 1920-8G (JG920A)";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl838x_hpe_1920.dtsi"
-
-/ {
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <0>;
- };
-
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-0 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>;
- // tx-fault and tx-disable unconnected
- };
-
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
- // tx-fault and tx-disable unconnected
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- port@24 {
- reg = <24>;
- label = "lan9";
- phy-handle = <&phy24>;
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp0>;
- };
-
- port@26 {
- reg = <26>;
- label = "lan10";
- phy-handle = <&phy26>;
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp1>;
- };
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "realtek,rtl838x-soc";
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- keys {
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
-
- compatible = "gpio-keys";
-
- mode {
- label = "reset";
- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
- open-source;
- };
-
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <31>;
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x00e0000>;
- read-only;
- };
-
- partition@e0000 {
- label = "u-boot-env";
- reg = <0x00e0000 0x0010000>;
- };
-
- partition@f0000 {
- label = "u-boot-env2";
- reg = <0x00f0000 0x0010000>;
- };
-
- partition@100000 {
- label = "jffs";
- reg = <0x0100000 0x0100000>;
- read-only;
- };
-
- partition@200000 {
- label = "jffs2";
- reg = <0x0200000 0x0100000>;
- read-only;
- };
-
- firmware: partition@300000 {
- label = "firmware";
- compatible = "openwrt,uimage", "denx,uimage";
- reg = <0x0300000 0x0e80000>;
- };
-
- partition@1180000 {
- label = "runtime2";
- reg = <0x1180000 0x0e80000>;
- read-only;
- };
- };
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit.dtsi"
-
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "netgear,gs108t-v3", "realtek,rtl838x-soc";
- model = "Netgear GS108T v3";
-
- aliases {
- led-boot = &led_power_green;
- led-failsafe = &led_power_amber;
- led-running = &led_power_green;
- led-upgrade = &led_power_amber;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_amber: led-0 {
- label = "amber:power";
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_POWER;
- gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
- };
-
- led_power_green: led-1 {
- label = "green:power";
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&firmware {
- openwrt,ih-magic = <0x4e474520>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit.dtsi"
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "netgear,gs110tpp-v1", "realtek,rtl838x-soc";
- model = "Netgear GS110TPP v1";
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_red;
- led-running = &led_status_green;
- led-upgrade = &led_status_blue;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_red: led-0 {
- label = "red:status";
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
- };
-
- led_status_green: led-1 {
- label = "green:status";
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
- };
-
- led_status_blue: led-2 {
- label = "blue:status";
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&firmware {
- openwrt,ih-magic = <0x4e474520>;
-};
-
-&uart1 {
- status = "okay";
-};
-
-&mdio {
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
-};
-
-&switch0 {
- ports {
- SWITCH_PORT(16, 9, qsgmii)
- SWITCH_PORT(17, 10, qsgmii)
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit.dtsi"
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "netgear,gs110tup-v1", "realtek,rtl838x-soc";
- model = "Netgear GS110TUP v1";
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_red;
- led-running = &led_status_green;
- led-upgrade = &led_status_blue;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_red: led-0 {
- label = "red:status";
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
- };
-
- led_status_green: led-1 {
- label = "green:status";
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
- };
-
- led_status_blue: led-2 {
- label = "blue:status";
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&firmware {
- openwrt,ih-magic = <0x4e474720>;
-};
-
-&uart1 {
- status = "okay";
-};
-
-&mdio {
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(24)
-};
-
-&switch0 {
- ports {
- SWITCH_PORT(16, 9, qsgmii)
- SWITCH_SFP_PORT(24, 10, rgmii-id)
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit.dtsi"
-
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "netgear,gs308t-v1", "realtek,rtl838x-soc";
- model = "Netgear GS308T v1";
-
- aliases {
- led-boot = &led_power_green;
- led-failsafe = &led_power_amber;
- led-running = &led_power_green;
- led-upgrade = &led_power_amber;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_amber: led-0 {
- label = "amber:power";
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_POWER;
- gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
- };
-
- led_power_green: led-1 {
- label = "green:power";
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&firmware {
- openwrt,ih-magic = <0x4e474335>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_netgear_gigabit.dtsi"
-
-/ {
- compatible = "netgear,gs310tp-v1", "realtek,rtl838x-soc";
- model = "Netgear GS310TP v1";
-
-};
-
-&firmware {
- openwrt,ih-magic = <0x4e474335>;
-};
-
-&uart1 {
- status = "okay";
-};
-
-&mdio {
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
-};
-
-&switch0 {
- ports {
- SWITCH_SFP_PORT(24, 9, rgmii-id)
- SWITCH_SFP_PORT(26, 10, rgmii-id)
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- compatible = "panasonic,m8eg-pn28080k", "realtek,rtl8380-soc";
- model = "Panasonic Switch-M8eG PN28080K";
-
- aliases {
- led-boot = &led_status_eco_green;
- led-failsafe = &led_status_eco_amber;
- led-running = &led_status_eco_green;
- led-upgrade = &led_status_eco_green;
- };
-
- sfp0: sfp-p9 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&leds {
- led_status_eco_amber: led-5 {
- label = "amber:status_eco";
- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_STATUS;
- function-enumerator = <1>;
- };
-
- led_status_eco_green: led-6 {
- label = "green:status_eco";
- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- function-enumerator = <2>;
- };
-};
-
-&i2c_gpio_0 {
- scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&i2c_gpio_1 {
- scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&gpio1 {
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gpio0>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
-};
-
-&gpio2 {
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gpio0>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
-};
-
-&i2c_switch {
- i2c0: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-};
-
-ðernet0 {
- mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- INTERNAL_PHY(24)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- port@24 {
- reg = <24>;
- label = "lan9";
- phy-mode = "1000base-x";
- phy-handle = <&phy24>;
- managed = "in-band-status";
- sfp = <&sfp0>;
- };
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_tplink_sg2xxx.dtsi"
-
-/ {
- compatible = "tplink,sg2008p-v1", "realtek,rtl838x-soc";
- model = "TP-Link SG2008P v1";
-};
-
-&tps23861_20 {
- status = "disabled";
-};
-
-&phy24 {
- status = "disabled";
-};
-
-&phy26 {
- status = "disabled";
-};
-
-&port24 {
- status = "disabled";
-};
-
-&port26 {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_tplink_sg2xxx.dtsi"
-
-/ {
- compatible = "tplink,sg2210p-v3", "realtek,rtl838x-soc";
- model = "TP-Link SG2210P v3";
-};
-
-&port24 {
- label = "lan-sfp2";
-};
-
-&port26 {
- label = "lan-sfp1";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- label-mac-device = ðernet0;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x10000000>;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: led-0 {
- label = "green:power";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- tps23861_20: tps23861@20 {
- compatible = "ti,tps23861";
- reg = <0x20>;
- shunt-resistor-micro-ohms = <255000>;
- };
-
- tps23861_28: tps23861@28 {
- compatible = "ti,tps23861";
- reg = <0x28>;
- shunt-resistor-micro-ohms = <255000>;
- };
- };
-
- watchdog {
- compatible = "linux,wdt-gpio";
- gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
- hw_algo = "toggle";
- /* SGM706 specs: typical 1.6s, but minimum 1.0s. */
- hw_margin_ms = <1000>;
- };
-};
-
-&gpio0 {
- watchdog-enable {
- gpio-hog;
- gpios = <14 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "watchdog-enable";
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0xe0000>;
- read-only;
- };
- partition@e0000 {
- label = "u-boot-env";
- reg = <0xe0000 0x20000>;
- };
- partition@100000 {
- compatible = "denx,uimage";
- label = "firmware";
- reg = <0x100000 0x1a00000>;
- };
- partition@1b00000 {
- label = "usrappfs";
- reg = <0x1b00000 0x400000>;
- };
- partition@1f00000 {
- label = "para";
- reg = <0x1f00000 0x100000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- factory_macaddr: macaddr@fdff4 {
- reg = <0xfdff4 0x6>;
- };
- };
- };
- };
- };
-};
-
-ðernet0 {
- nvmem-cells = <&factory_macaddr>;
- nvmem-cell-names = "mac-address";
-
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(15, 1, internal)
- SWITCH_PORT(14, 2, internal)
- SWITCH_PORT(13, 3, internal)
- SWITCH_PORT(12, 4, internal)
- SWITCH_PORT(11, 5, internal)
- SWITCH_PORT(10, 6, internal)
- SWITCH_PORT(9, 7, internal)
- SWITCH_PORT(8, 8, internal)
-
- SWITCH_SFP_PORT(24, 9, 1000base-x)
- SWITCH_SFP_PORT(26, 10, 1000base-x)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-10hp", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-10HP Switch";
-
- /* i2c of the left SFP cage: port 9 */
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-p9 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- };
-
- /* i2c of the right SFP cage: port 10 */
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-p10 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-&mdio {
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
-};
-
-&switch0 {
- ports {
- port@24 {
- reg = <24>;
- label = "lan9";
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp0>;
- };
-
- port@26 {
- reg = <26>;
- label = "lan10";
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp1>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-8", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-8 Switch";
-};
-
-&gpio1 {
- /delete-node/ poe_enable;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-8hp-v1", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-8HP v1 Switch";
-};
-
-&uart1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-8hp-v2", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-8HP v2 Switch";
-};
-
-&uart1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- keys {
- compatible = "gpio-keys-polled";
- poll-interval = <20>;
-
- reset {
- label = "reset";
- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
- compatible = "gpio-leds";
-
- led_sys: sys {
- label = "green:sys";
- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <0>;
-
- poe_enable {
- gpio-hog;
- gpios = <13 GPIO_ACTIVE_HIGH>;
- output-high;
- };
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "u-boot-env";
- reg = <0x40000 0x10000>;
- read-only;
- };
- partition@50000 {
- label = "u-boot-env2";
- reg = <0x50000 0x10000>;
- };
- partition@60000 {
- label = "jffs";
- reg = <0x60000 0x100000>;
- };
- partition@160000 {
- label = "jffs2";
- reg = <0x160000 0x100000>;
- };
- partition@b260000 {
- label = "firmware";
- reg = <0x260000 0x6d0000>;
- compatible = "openwrt,uimage", "denx,uimage";
- openwrt,ih-magic = <0x83800000>;
- };
- partition@930000 {
- label = "runtime2";
- reg = <0x930000 0x6d0000>;
- };
- };
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
- model = "ALLNET ALL-SG8208M";
-
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- keys {
- compatible = "gpio-keys-polled";
- poll-interval = <20>;
-
- /* is this pin 3 on the external RTL8231 (&gpio1)? */
- /*reset {
- label = "reset";
- gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };*/
- };
-
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
- compatible = "gpio-leds";
-
- led_sys: sys {
- label = "green:sys";
- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- };
- // GPIO 25: power on/off all port leds
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "u-boot-env";
- reg = <0x80000 0x10000>;
- read-only;
- };
-
- partition@90000 {
- label = "u-boot-env2";
- reg = <0x90000 0x10000>;
- };
-
- partition@a0000 {
- label = "jffs";
- reg = <0xa0000 0x100000>;
- };
-
- partition@1a0000 {
- label = "jffs2";
- reg = <0x1a0000 0x100000>;
- };
-
- partition@2a0000 {
- label = "firmware";
- reg = <0x2a0000 0xd60000>;
- compatible = "openwrt,uimage", "denx,uimage";
- openwrt,ih-magic = <0x00000006>;
- };
- };
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "apresia,aplgs120gtss", "realtek,rtl8382-soc";
- model = "APRESIA ApresiaLightGS120GT-SS";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x10000000>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: led-0 {
- label = "green:pwr";
- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- };
-
- led-1 {
- label = "red:loop";
- gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_FAULT;
- };
-
- /* LED chip is soldered, but no hole on the case */
- led-2 {
- label = "green:unused";
- gpios = <&gpio1 36 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- };
- };
-
- keys {
- compatible = "gpio-keys-polled";
- poll-interval = <20>;
-
- reset {
- label = "reset";
- gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
- open-source;
- };
-
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <0>;
- };
-
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c2: i2c-gpio-2 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c3: i2c-gpio-3 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- /* 4x TX-Disable lines are provided by RTL8214FC */
- sfp0: sfp-p17 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
- };
-
- sfp1: sfp-p18 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- };
-
- sfp2: sfp-p19 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c3>;
- los-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>;
- };
-
- sfp3: sfp-p20 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c2>;
- los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
- };
-};
-
-&gpio0 {
- rtl8231_reset {
- gpio-hog;
- gpios = <1 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "rtl8231-reset";
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "u-boot-env";
- reg = <0x80000 0x40000>;
- };
-
- partition@c0000 {
- label = "u-boot-env2";
- reg = <0xc0000 0x40000>;
- };
-
- partition@100000 {
- compatible = "openwrt,uimage", "denx,uimage";
- label = "firmware";
- reg = <0x100000 0xe80000>;
- openwrt,ih-magic = <0x12345000>;
- };
-
- partition@f80000 {
- label = "firmware2";
- reg = <0xf80000 0xe80000>;
- };
-
- partition@1e00000 {
- label = "jffs2";
- reg = <0x1e00000 0x200000>;
- read-only;
- };
- };
- };
-};
-
-ðernet0 {
- mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- EXTERNAL_SFP_PHY_FULL(24, 0)
- EXTERNAL_SFP_PHY_FULL(25, 1)
- EXTERNAL_SFP_PHY_FULL(26, 2)
- EXTERNAL_SFP_PHY_FULL(27, 3)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(24, 17, qsgmii)
- SWITCH_PORT(25, 18, qsgmii)
- SWITCH_PORT(26, 19, qsgmii)
- SWITCH_PORT(27, 20, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_d-link_dgs-1210_common.dtsi"
-
-/ {
- compatible = "d-link,dgs-1210-10p", "realtek,rtl838x-soc";
- model = "D-Link DGS-1210-10P";
-
- /* i2c of the left SFP cage: port 9 */
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-p9 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- };
-
- /* i2c of the right SFP cage: port 10 */
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-p10 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- };
-
- keys {
- compatible = "gpio-keys-polled";
- poll-interval = <20>;
-
- mode {
- label = "mode";
- gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- };
-
- reset {
- label = "reset";
- gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- link_act {
- label = "green:link_act";
- gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
- };
-
- poe {
- label = "green:poe";
- gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
- };
-
- poe_max {
- label = "yellow:poe_max";
- gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <0>;
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- port@24 {
- reg = <24>;
- label = "lan9";
- phy-handle = <&phy24>;
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp0>;
- };
-
- port@26 {
- reg = <26>;
- label = "lan10";
- phy-handle = <&phy26>;
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp1>;
- };
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_d-link_dgs-1210_common.dtsi"
-
-/ {
- compatible = "d-link,dgs-1210-16", "realtek,rtl838x-soc";
- model = "D-Link DGS-1210-16";
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- EXTERNAL_SFP_PHY(24)
- EXTERNAL_SFP_PHY(25)
- EXTERNAL_SFP_PHY(26)
- EXTERNAL_SFP_PHY(27)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(24, 17, qsgmii)
- SWITCH_PORT(25, 18, qsgmii)
- SWITCH_PORT(26, 19, qsgmii)
- SWITCH_PORT(27, 20, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_d-link_dgs-1210_common.dtsi"
-#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
-
-/ {
- compatible = "d-link,dgs-1210-20", "realtek,rtl838x-soc";
- model = "D-Link DGS-1210-20";
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- EXTERNAL_SFP_PHY(24)
- EXTERNAL_SFP_PHY(25)
- EXTERNAL_SFP_PHY(26)
- EXTERNAL_SFP_PHY(27)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(24, 17, qsgmii)
- SWITCH_PORT(25, 18, qsgmii)
- SWITCH_PORT(26, 19, qsgmii)
- SWITCH_PORT(27, 20, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_d-link_dgs-1210_common.dtsi"
-#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
-#include "rtl8382_d-link_dgs-1210-28_common.dtsi"
-
-/ {
- compatible = "d-link,dgs-1210-28", "realtek,rtl838x-soc";
- model = "D-Link DGS-1210-28";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- EXTERNAL_SFP_PHY(24)
- EXTERNAL_SFP_PHY(25)
- EXTERNAL_SFP_PHY(26)
- EXTERNAL_SFP_PHY(27)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- SWITCH_PORT(24, 25, qsgmii)
- SWITCH_PORT(25, 26, qsgmii)
- SWITCH_PORT(26, 27, qsgmii)
- SWITCH_PORT(27, 28, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_d-link_dgs-1210_common.dtsi"
-#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
-#include "rtl8382_d-link_dgs-1210-28_common.dtsi"
-
-/ {
- compatible = "d-link,dgs-1210-28mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc";
- model = "D-Link DGS-1210-28MP F";
-};
-
-&leds {
- link_act {
- label = "green:link_act";
- gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
- };
-
- poe {
- label = "green:poe";
- gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
- };
-
- poe_max {
- label = "yellow:poe_max";
- gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
- };
-};
-
-&keys {
- mode {
- label = "mode";
- gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
-};
-
-&uart1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl8382_hpe_1920.dtsi"
-
-/ {
- compatible = "hpe,1920-16g", "realtek,rtl838x-soc";
- model = "HPE 1920-16G (JG923A)";
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- SWITCH_PORT(16, 9, qsgmii)
- SWITCH_PORT(17, 10, qsgmii)
- SWITCH_PORT(18, 11, qsgmii)
- SWITCH_PORT(19, 12, qsgmii)
- SWITCH_PORT(20, 13, qsgmii)
- SWITCH_PORT(21, 14, qsgmii)
- SWITCH_PORT(22, 15, qsgmii)
- SWITCH_PORT(23, 16, qsgmii)
-
- SWITCH_PORT(24, 17, qsgmii)
- SWITCH_PORT(25, 18, qsgmii)
- SWITCH_PORT(26, 19, qsgmii)
- SWITCH_PORT(27, 20, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl8382_hpe_1920.dtsi"
-
-/ {
- compatible = "hpe,1920-24g", "realtek,rtl838x-soc";
- model = "HPE 1920-24G (JG924A)";
-};
-
-&mdio {
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- SWITCH_PORT(24, 25, qsgmii)
- SWITCH_PORT(25, 26, qsgmii)
- SWITCH_PORT(26, 27, qsgmii)
- SWITCH_PORT(27, 28, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl838x_hpe_1920.dtsi"
-
-/ {
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <0>;
- };
-
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-0 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
- // tx-fault unconnected
- // tx-disable connected to RTL8214FC
- };
-
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-1 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>;
- // tx-fault unconnected
- // tx-disable connected to RTL8214FC
- };
-
- i2c2: i2c-gpio-2 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp2: sfp-2 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c2>;
- los-gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
- // tx-fault unconnected
- // tx-disable connected to RTL8214FC
- };
-
- i2c3: i2c-gpio-3 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp3: sfp-3 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c3>;
- los-gpio = <&gpio1 34 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 33 GPIO_ACTIVE_LOW>;
- // tx-fault unconnected
- // tx-disable connected to RTL8214FC
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- EXTERNAL_SFP_PHY_FULL(24, 0)
- EXTERNAL_SFP_PHY_FULL(25, 1)
- EXTERNAL_SFP_PHY_FULL(26, 2)
- EXTERNAL_SFP_PHY_FULL(27, 3)
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
- model = "INABA Abaniact AML2-17GP";
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- keys {
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
-
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "u-boot-env";
- reg = <0x80000 0x10000>;
- read-only;
- };
-
- partition@90000 {
- label = "u-boot-env2";
- reg = <0x90000 0x10000>;
- };
-
- partition@a0000 {
- label = "jffs2_cfg";
- reg = <0xa0000 0x400000>;
- read-only;
- };
-
- partition@4a0000 {
- label = "jffs2_log";
- reg = <0x4a0000 0x100000>;
- read-only;
- };
-
- partition@5a0000 {
- compatible = "openwrt,uimage", "denx,uimage";
- label = "firmware";
- reg = <0x5a0000 0xd30000>;
- openwrt,ih-magic = <0x83800000>;
- };
-
- partition@12d0000 {
- label = "runtime2";
- reg = <0x12d0000 0xd30000>;
- };
- };
- };
-};
-
-ðernet0 {
- mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- EXTERNAL_PHY(24)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- SWITCH_PORT(16, 9, qsgmii)
- SWITCH_PORT(17, 10, qsgmii)
- SWITCH_PORT(18, 11, qsgmii)
- SWITCH_PORT(19, 12, qsgmii)
- SWITCH_PORT(20, 13, qsgmii)
- SWITCH_PORT(21, 14, qsgmii)
- SWITCH_PORT(22, 15, qsgmii)
- SWITCH_PORT(23, 16, qsgmii)
-
- port@24 {
- reg = <24>;
- label = "wan";
- phy-handle = <&phy24>;
- phy-mode = "qsgmii";
- };
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "iodata,bsh-g24mb", "realtek,rtl838x-soc";
- model = "I-O DATA BSH-G24MB";
-
- aliases {
- led-boot = &led_sys_loop;
- led-failsafe = &led_sys_loop;
- led-upgrade = &led_sys_loop;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
- compatible = "gpio-leds";
-
- led_sys_loop: led {
- label = "red:sys_loop";
- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_STATUS;
- };
- };
-
- keys {
- compatible = "gpio-keys-polled";
- poll-interval = <20>;
-
- reset {
- label = "reset";
- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <0>;
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "u-boot-env";
- reg = <0x80000 0x10000>;
- read-only;
- };
-
- partition@90000 {
- label = "u-boot-env2";
- reg = <0x90000 0x10000>;
- };
-
- partition@a0000 {
- label = "jffs2_cfg";
- reg = <0xa0000 0x100000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "jffs2_log";
- reg = <0x1a0000 0x100000>;
- read-only;
- };
-
- /*
- * use 2x OS partitions in OpenWrt
- *
- * 0x2A0000-0x94FFFF: RUNTIME
- * 0x950000-0xFFFFFF: RUNTIME2 (not used in stock)
- */
- partition@2a0000 {
- compatible = "openwrt,uimage", "denx,uimage";
- label = "firmware";
- reg = <0x2a0000 0xd60000>;
- openwrt,ih-magic = <0x83800013>;
- };
- };
- };
-};
-
-ðernet0 {
- mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- compatible = "panasonic,m16eg-pn28160k", "realtek,rtl8382-soc";
- model = "Panasonic Switch-M16eG PN28160K";
-
- aliases {
- led-boot = &led_status_eco_green;
- led-failsafe = &led_status_eco_amber;
- led-running = &led_status_eco_green;
- led-upgrade = &led_status_eco_green;
- };
-
- /*
- * sfp0/1 are "combo" port with each TP port (23/24), and they are
- * connected to the RTL8218FB. Currently, there is no support for
- * the chip and only TP ports work by the RTL8218D support.
- */
- sfp0: sfp-p23 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-
- sfp1: sfp-p24 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&leds {
- led_status_eco_amber: led-5 {
- label = "amber:status_eco";
- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_STATUS;
- function-enumerator = <1>;
- };
-
- led_status_eco_green: led-6 {
- label = "green:status_eco";
- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- function-enumerator = <2>;
- };
-};
-
-&i2c_gpio_0 {
- scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&i2c_gpio_1 {
- scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&gpio2 {
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gpio0>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
-
- /*
- * GPIO12 (IO1_4): RTL8218FB
- *
- * This GPIO pin should be specified as "reset-gpio" in mdio node, but
- * RTL8218FB phy won't be configured on RTL8218D support in the current
- * phy driver. So, ethernet ports on the phy will be broken after hard-
- * resetting.
- * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
- * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
- * by resetting.
- */
- ext_switch_reset {
- gpio-hog;
- gpios = <12 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "ext-switch-reset";
- };
-};
-
-&i2c_switch {
- i2c0: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- i2c1: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-};
-
-ðernet0 {
- mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- /* RTL8218FB */
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(8, 1, internal)
- SWITCH_PORT(9, 2, internal)
- SWITCH_PORT(10, 3, internal)
- SWITCH_PORT(11, 4, internal)
- SWITCH_PORT(12, 5, internal)
- SWITCH_PORT(13, 6, internal)
- SWITCH_PORT(14, 7, internal)
- SWITCH_PORT(15, 8, internal)
-
- SWITCH_PORT(16, 9, qsgmii)
- SWITCH_PORT(17, 10, qsgmii)
- SWITCH_PORT(18, 11, qsgmii)
- SWITCH_PORT(19, 12, qsgmii)
- SWITCH_PORT(20, 13, qsgmii)
- SWITCH_PORT(21, 14, qsgmii)
- SWITCH_PORT(22, 15, qsgmii)
- SWITCH_PORT(23, 16, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- compatible = "panasonic,m24eg-pn28240k", "realtek,rtl8382-soc";
- model = "Panasonic Switch-M24eG PN28240K";
-
- aliases {
- led-boot = &led_status_eco_green;
- led-failsafe = &led_status_eco_amber;
- led-running = &led_status_eco_green;
- led-upgrade = &led_status_eco_green;
- };
-
- /*
- * sfp0/1 are "combo" port with each TP port (23/24), and they are
- * connected to the RTL8218FB. Currently, there is no support for
- * the chip and only TP ports work by the RTL8218D support.
- */
- sfp0: sfp-p23 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-
- sfp1: sfp-p24 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&leds {
- led_status_eco_amber: led-5 {
- label = "amber:status_eco";
- gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_STATUS;
- function-enumerator = <1>;
- };
-
- led_status_eco_green: led-6 {
- label = "green:status_eco";
- gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- function-enumerator = <2>;
- };
-};
-
-&i2c_gpio_0 {
- scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&i2c_gpio_1 {
- scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&gpio2 {
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gpio0>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
-
- /*
- * GPIO12 (IO1_4): RTL8218B + RTL8218FB
- *
- * This GPIO pin should be specified as "reset-gpio" in mdio node,
- * but the current configuration of RTL8218B phy in the phy driver
- * seems to be incomplete and RTL8218FB phy won't be configured on
- * RTL8218D support. So, ethernet ports on these phys will be broken
- * after hard-resetting.
- * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
- * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
- * by resetting.
- */
- ext_switch_reset {
- gpio-hog;
- gpios = <12 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "ext-switch-reset";
- };
-};
-
-&i2c_switch {
- i2c0: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- i2c1: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-};
-
-ðernet0 {
- mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- /* RTL8218FB */
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl838x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "tplink,t1600g-28ts-v3", "realtek,rtl838x-soc";
- model = "TP-Link T1600G-28TS v3";
-
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- label-mac-device = ðernet0;
- };
-
- chosen {
- stdout-path = "serial0:38400n8";
- };
-
- leds {
- pinctrl-names = "default";
- compatible = "gpio-leds";
-
- led_sys: led-0 {
- label = "green:sys";
- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x10000000>;
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0xe0000>;
- read-only;
- };
- partition@e0000 {
- label = "u-boot-env";
- reg = <0xe0000 0x20000>;
- };
- partition@100000 {
- compatible = "denx,uimage";
- label = "firmware";
- reg = <0x100000 0x1a00000>;
- };
- partition@1b00000 {
- label = "usrappfs";
- reg = <0x1b00000 0x400000>;
- };
- partition@1f00000 {
- label = "para";
- reg = <0x1f00000 0x100000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- factory_macaddr: macaddr@fdff4 {
- reg = <0xfdff4 0x6>;
- };
- };
- };
- };
- };
-};
-
-ðernet0 {
- nvmem-cells = <&factory_macaddr>;
- nvmem-cell-names = "mac-address";
-
- mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- INTERNAL_PHY(8)
- INTERNAL_PHY(9)
- INTERNAL_PHY(10)
- INTERNAL_PHY(11)
- INTERNAL_PHY(12)
- INTERNAL_PHY(13)
- INTERNAL_PHY(14)
- INTERNAL_PHY(15)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-16", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-16";
-};
-
-&mdio {
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-};
-
-&switch0 {
- ports {
- SWITCH_PORT(16, 9, qsgmii)
- SWITCH_PORT(17, 10, qsgmii)
- SWITCH_PORT(18, 11, qsgmii)
- SWITCH_PORT(19, 12, qsgmii)
- SWITCH_PORT(20, 13, qsgmii)
- SWITCH_PORT(21, 14, qsgmii)
- SWITCH_PORT(22, 15, qsgmii)
- SWITCH_PORT(23, 16, qsgmii)
- };
-};
-
-&gpio1 {
- /delete-node/ poe_enable;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-24-v1", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-24 v1";
-
- memory@0 {
- reg = <0x0 0x4000000>;
- };
-
- /* i2c of the left SFP cage: port 25 */
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-p25 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- };
-
- /* i2c of the right SFP cage: port 26 */
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-p26 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-&mdio {
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
-};
-
-&switch0 {
- ports {
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- port@24 {
- reg = <24>;
- label = "lan25";
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp0>;
- };
-
- port@26 {
- reg = <26>;
- label = "lan26";
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp1>;
- };
- };
-};
-
-&gpio1 {
- /delete-node/ poe_enable;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-24e", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-24E";
-};
-
-&mdio {
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-};
-
-&switch0 {
- ports {
- SWITCH_PORT(1, 1, qsgmii)
- SWITCH_PORT(0, 2, qsgmii)
- SWITCH_PORT(3, 3, qsgmii)
- SWITCH_PORT(2, 4, qsgmii)
- SWITCH_PORT(5, 5, qsgmii)
- SWITCH_PORT(4, 6, qsgmii)
- SWITCH_PORT(7, 7, qsgmii)
- SWITCH_PORT(6, 8, qsgmii)
-
- SWITCH_PORT(9, 9, internal)
- SWITCH_PORT(8, 10, internal)
- SWITCH_PORT(11, 11, internal)
- SWITCH_PORT(10, 12, internal)
- SWITCH_PORT(13, 13, internal)
- SWITCH_PORT(12, 14, internal)
- SWITCH_PORT(15, 15, internal)
- SWITCH_PORT(14, 16, internal)
-
- SWITCH_PORT(17, 17, qsgmii)
- SWITCH_PORT(16, 18, qsgmii)
- SWITCH_PORT(19, 19, qsgmii)
- SWITCH_PORT(18, 20, qsgmii)
- SWITCH_PORT(21, 21, qsgmii)
- SWITCH_PORT(20, 22, qsgmii)
- SWITCH_PORT(23, 23, qsgmii)
- SWITCH_PORT(22, 24, qsgmii)
- };
-};
-
-&gpio1 {
- /delete-node/ poe_enable;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-24hp-v1", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-24HP v1";
-
- memory@0 {
- reg = <0x0 0x4000000>;
- };
-
- /* i2c of the left SFP cage: port 25 */
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-p25 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- };
-
- /* i2c of the right SFP cage: port 26 */
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-p26 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-&mdio {
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
-};
-
-&switch0 {
- ports {
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- port@24 {
- reg = <24>;
- label = "lan25";
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp0>;
- };
-
- port@26 {
- reg = <26>;
- label = "lan26";
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp1>;
- };
- };
-};
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "rtl8380_zyxel_gs1900.dtsi"
-
-/ {
- compatible = "zyxel,gs1900-24hp-v2", "realtek,rtl838x-soc";
- model = "ZyXEL GS1900-24HP v2 Switch";
-
- /* i2c of the left SFP cage: port 25 */
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-p25 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- };
-
- /* i2c of the right SFP cage: port 26 */
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-p26 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-&mdio {
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- INTERNAL_PHY(24)
- INTERNAL_PHY(26)
-};
-
-&switch0 {
- ports {
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, internal)
- SWITCH_PORT(9, 10, internal)
- SWITCH_PORT(10, 11, internal)
- SWITCH_PORT(11, 12, internal)
- SWITCH_PORT(12, 13, internal)
- SWITCH_PORT(13, 14, internal)
- SWITCH_PORT(14, 15, internal)
- SWITCH_PORT(15, 16, internal)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
-
- port@24 {
- reg = <24>;
- label = "lan25";
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp0>;
- };
-
- port@26 {
- reg = <26>;
- label = "lan26";
- phy-mode = "1000base-x";
- managed = "in-band-status";
- sfp = <&sfp1>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/clock/rtl83xx-clk.h>
-
-/dts-v1/;
-
-#define STRINGIZE(s) #s
-#define LAN_LABEL(p, s) STRINGIZE(p ## s)
-#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
-
-#define INTERNAL_PHY(n) \
- phy##n: ethernet-phy@##n { \
- reg = <##n>; \
- compatible = "ethernet-phy-ieee802.3-c22"; \
- phy-is-integrated; \
- };
-
-#define EXTERNAL_PHY(n) \
- phy##n: ethernet-phy@##n { \
- reg = <##n>; \
- compatible = "ethernet-phy-ieee802.3-c22"; \
- };
-
-#define EXTERNAL_SFP_PHY(n) \
- phy##n: ethernet-phy@##n { \
- compatible = "ethernet-phy-ieee802.3-c22"; \
- sfp; \
- media = "fibre"; \
- reg = <##n>; \
- };
-
-#define EXTERNAL_SFP_PHY_FULL(n, s) \
- phy##n: ethernet-phy@##n { \
- compatible = "ethernet-phy-ieee802.3-c22"; \
- sfp = <&sfp##s>; \
- reg = <##n>; \
- };
-
-#define SWITCH_PORT(n, s, m) \
- port##n: port@##n { \
- reg = <##n>; \
- label = SWITCH_PORT_LABEL(s) ; \
- phy-handle = <&phy##n>; \
- phy-mode = #m ; \
- };
-
-#define SWITCH_SFP_PORT(n, s, m) \
- port##n: port@##n { \
- reg = <##n>; \
- label = SWITCH_PORT_LABEL(s) ; \
- phy-handle = <&phy##n>; \
- phy-mode = #m ; \
- fixed-link { \
- speed = <1000>; \
- full-duplex; \
- }; \
- };
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- compatible = "realtek,rtl838x-soc";
-
- osc: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- ccu: clock-controller {
- compatible = "realtek,rtl8380-clock";
- #clock-cells = <1>;
- clocks = <&osc>;
- clock-names = "ref_clk";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "mips,mips4KEc";
- reg = <0>;
- clocks = <&ccu CLK_CPU>;
- operating-points-v2 = <&cpu_opp_table>;
- };
- };
-
- cpu_opp_table: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <325000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <350000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <375000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <400000000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <425000000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <450000000>;
- };
- opp06 {
- opp-hz = /bits/ 64 <475000000>;
- };
- opp07 {
- opp-hz = /bits/ 64 <500000000>;
- };
- };
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- };
-
- cpuintc: cpuintc {
- compatible = "mti,cpu-interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x18000000 0x10000>;
-
- intc: interrupt-controller@3000 {
- compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
- reg = <0x3000 0x18>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&cpuintc>;
- interrupts = <2>, <3>, <4>, <5>, <6>;
- };
-
- spi0: spi@1200 {
- compatible = "realtek,rtl8380-spi";
- reg = <0x1200 0x100>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- timer0: timer@3100 {
- compatible = "realtek,rtl8380-timer", "realtek,otto-timer";
- reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
- <0x3130 0x10>, <0x3140 0x10>;
-
- interrupt-parent = <&intc>;
- interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
- clocks = <&ccu CLK_LXB>;
- };
-
- uart0: uart@2000 {
- compatible = "ns16550a";
- reg = <0x2000 0x100>;
-
- clocks = <&ccu CLK_LXB>;
-
- interrupt-parent = <&intc>;
- interrupts = <31 1>;
-
- reg-io-width = <1>;
- reg-shift = <2>;
- fifo-size = <1>;
- no-loopback-test;
- };
-
- uart1: uart@2100 {
- pinctrl-names = "default";
- pinctrl-0 = <&enable_uart1>;
-
- compatible = "ns16550a";
- reg = <0x2100 0x100>;
-
- clocks = <&ccu CLK_LXB>;
-
- interrupt-parent = <&intc>;
- interrupts = <30 0>;
-
- reg-io-width = <1>;
- reg-shift = <2>;
- fifo-size = <1>;
- no-loopback-test;
-
- status = "disabled";
- };
-
- watchdog0: watchdog@3150 {
- compatible = "realtek,rtl8380-wdt";
- reg = <0x3150 0xc>;
-
- realtek,reset-mode = "soc";
-
- clocks = <&ccu CLK_LXB>;
- timeout-sec = <30>;
-
- interrupt-parent = <&intc>;
- interrupt-names = "phase1", "phase2";
- interrupts = <19 3>, <18 4>;
- };
-
- gpio0: gpio-controller@3500 {
- compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
- reg = <0x3500 0x20>;
-
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <24>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupts = <23 3>;
- };
- };
-
- pinmux: pinmux@1b001000 {
- compatible = "pinctrl-single";
- reg = <0x1b001000 0x4>;
-
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x1>;
- #pinctrl-cells = <2>;
-
- enable_uart1: pinmux_enable_uart1 {
- pinctrl-single,bits = <0x0 0x10 0x10>;
- };
- };
-
- /* LED_GLB_CTRL */
- pinmux_led: pinmux@1b00a000 {
- compatible = "pinctrl-single";
- reg = <0x1b00a000 0x4>;
-
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x1>;
- #pinctrl-cells = <2>;
-
- /* enable GPIO 0 */
- pinmux_disable_sys_led: disable_sys_led {
- pinctrl-single,bits = <0x0 0x0 0x8000>;
- };
- };
-
- ethernet0: ethernet@1b00a300 {
- compatible = "realtek,rtl838x-eth";
- reg = <0x1b00a300 0x100>;
- interrupt-parent = <&intc>;
- interrupts = <24 3>;
- #interrupt-cells = <1>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- sram0: sram@9f000000 {
- compatible = "mmio-sram";
- reg = <0x9f000000 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x9f000000 0x10000>;
- };
-
- switch0: switch@1b000000 {
- compatible = "realtek,rtl83xx-switch";
-
- interrupt-parent = <&intc>;
- interrupts = <20 2>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- chosen {
- stdout-path = "serial0:38400n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- watchdog1: watchdog {
- // PT7A7514
- compatible = "linux,wdt-gpio";
- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- hw_algo = "toggle";
- hw_margin_ms = <1000>;
- always-running;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
- };
-};
-
-&watchdog0 {
- status = "disabled";
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootware_basic";
- reg = <0x0 0x50000>;
- read-only;
- };
-
- partition@60000 {
- label = "bootware_data";
- reg = <0x60000 0x30000>;
- read-only;
- };
-
- partition@90000 {
- label = "bootware_extend";
- reg = <0x90000 0x40000>;
- read-only;
- };
-
- partition@100000 {
- label = "bootware_basic_backup";
- reg = <0x100000 0x50000>;
- read-only;
- };
-
- partition@160000 {
- label = "bootware_data_backup";
- reg = <0x160000 0x30000>;
- read-only;
- };
-
- partition@190000 {
- label = "bootware_extend_backup";
- reg = <0x190000 0x40000>;
- read-only;
- };
-
- partition@300000 {
- label = "firmware";
- compatible = "h3c,vfs-firmware";
- reg = <0x300000 0x1cf0000>;
- };
-
- partition@1ff0000 {
- label = "factory";
- reg = <0x1ff0000 0x10000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl839x.dtsi"
-#include "rtl83xx_d-link_dgs-1210_common.dtsi"
-#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
-#include "rtl839x_d-link_dgs-1210_gpio.dtsi"
-
-/ {
- compatible = "d-link,dgs-1210-52", "realtek,rtl8393-soc";
- model = "D-Link DGS-1210-52";
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* External phy RTL8218B #1 */
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- /* External phy RTL8218B #2 */
- EXTERNAL_PHY(8)
- EXTERNAL_PHY(9)
- EXTERNAL_PHY(10)
- EXTERNAL_PHY(11)
- EXTERNAL_PHY(12)
- EXTERNAL_PHY(13)
- EXTERNAL_PHY(14)
- EXTERNAL_PHY(15)
-
- /* External phy RTL8218B #3 */
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- /* External phy RTL8218B #4 */
- EXTERNAL_PHY(24)
- EXTERNAL_PHY(25)
- EXTERNAL_PHY(26)
- EXTERNAL_PHY(27)
- EXTERNAL_PHY(28)
- EXTERNAL_PHY(29)
- EXTERNAL_PHY(30)
- EXTERNAL_PHY(31)
-
- /* External phy RTL8218B #5 */
- EXTERNAL_PHY(32)
- EXTERNAL_PHY(33)
- EXTERNAL_PHY(34)
- EXTERNAL_PHY(35)
- EXTERNAL_PHY(36)
- EXTERNAL_PHY(37)
- EXTERNAL_PHY(38)
- EXTERNAL_PHY(39)
-
- /* External phy RTL8218B #6 */
- EXTERNAL_PHY(40)
- EXTERNAL_PHY(41)
- EXTERNAL_PHY(42)
- EXTERNAL_PHY(43)
- EXTERNAL_PHY(44)
- EXTERNAL_PHY(45)
- EXTERNAL_PHY(46)
- EXTERNAL_PHY(47)
-
- /* External phy RTL8214FC */
- EXTERNAL_SFP_PHY_FULL(48, 0)
- EXTERNAL_SFP_PHY_FULL(49, 1)
- EXTERNAL_SFP_PHY_FULL(50, 2)
- EXTERNAL_SFP_PHY_FULL(51, 3)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, qsgmii)
- SWITCH_PORT(9, 10, qsgmii)
- SWITCH_PORT(10, 11, qsgmii)
- SWITCH_PORT(11, 12, qsgmii)
- SWITCH_PORT(12, 13, qsgmii)
- SWITCH_PORT(13, 14, qsgmii)
- SWITCH_PORT(14, 15, qsgmii)
- SWITCH_PORT(15, 16, qsgmii)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- SWITCH_PORT(24, 25, qsgmii)
- SWITCH_PORT(25, 26, qsgmii)
- SWITCH_PORT(26, 27, qsgmii)
- SWITCH_PORT(27, 28, qsgmii)
- SWITCH_PORT(28, 29, qsgmii)
- SWITCH_PORT(29, 30, qsgmii)
- SWITCH_PORT(30, 31, qsgmii)
- SWITCH_PORT(31, 32, qsgmii)
-
- SWITCH_PORT(32, 33, qsgmii)
- SWITCH_PORT(33, 34, qsgmii)
- SWITCH_PORT(34, 35, qsgmii)
- SWITCH_PORT(35, 36, qsgmii)
- SWITCH_PORT(36, 37, qsgmii)
- SWITCH_PORT(37, 38, qsgmii)
- SWITCH_PORT(38, 39, qsgmii)
- SWITCH_PORT(39, 40, qsgmii)
-
- SWITCH_PORT(40, 41, qsgmii)
- SWITCH_PORT(41, 42, qsgmii)
- SWITCH_PORT(42, 43, qsgmii)
- SWITCH_PORT(43, 44, qsgmii)
- SWITCH_PORT(44, 45, qsgmii)
- SWITCH_PORT(45, 46, qsgmii)
- SWITCH_PORT(46, 47, qsgmii)
- SWITCH_PORT(47, 48, qsgmii)
-
- SWITCH_PORT(48, 49, qsgmii)
- SWITCH_PORT(49, 50, qsgmii)
- SWITCH_PORT(50, 51, qsgmii)
- SWITCH_PORT(51, 52, qsgmii)
-
- /* CPU-Port */
- port@52 {
- ethernet = <ðernet0>;
- reg = <52>;
- phy-mode = "qsgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl839x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "netgear,gs750e", "realtek,rtl8393-soc";
- model = "Netgear GS750E";
-
- aliases {
- label-mac-device = ðernet0;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
- };
-
- virtual_flash {
- compatible = "mtd-concat";
-
- devices = <&fwconcat0>, <&fwconcat1>, <&fwconcat2>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "firmware";
- reg = <0x0 0x760000>;
- compatible = "openwrt,uimage", "denx,uimage";
- openwrt,ih-magic = <0x174e4741>;
- };
- };
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "u-boot-env";
- reg = <0x80000 0x10000>;
- read-only;
- };
-
- partition@90000 {
- label = "u-boot-env2";
- reg = <0x90000 0x10000>;
- read-only;
- };
-
- fwconcat1: partition@a0000 {
- label = "jffs2_cfg";
- reg = <0xa0000 0x80000>;
- };
-
- fwconcat2: partition@120000 {
- label = "jffs2_log";
- reg = <0x120000 0x80000>;
- };
-
- fwconcat0: partition@1a0000 {
- label = "runtime";
- reg = <0x1a0000 0x660000>;
- };
- };
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- // Switch doesn't come back properly after a reset so don't.
- // reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
-
- /* External phy RTL8218B #1 */
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- /* External phy RTL8218B #2 */
- EXTERNAL_PHY(8)
- EXTERNAL_PHY(9)
- EXTERNAL_PHY(10)
- EXTERNAL_PHY(11)
- EXTERNAL_PHY(12)
- EXTERNAL_PHY(13)
- EXTERNAL_PHY(14)
- EXTERNAL_PHY(15)
-
- /* External phy RTL8218B #3 */
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- /* External phy RTL8218B #4 */
- EXTERNAL_PHY(24)
- EXTERNAL_PHY(25)
- EXTERNAL_PHY(26)
- EXTERNAL_PHY(27)
- EXTERNAL_PHY(28)
- EXTERNAL_PHY(29)
- EXTERNAL_PHY(30)
- EXTERNAL_PHY(31)
-
- /* External phy RTL8218B #5 */
- EXTERNAL_PHY(32)
- EXTERNAL_PHY(33)
- EXTERNAL_PHY(34)
- EXTERNAL_PHY(35)
- EXTERNAL_PHY(36)
- EXTERNAL_PHY(37)
- EXTERNAL_PHY(38)
- EXTERNAL_PHY(39)
-
- /* External phy RTL8218B #6 */
- EXTERNAL_PHY(40)
- EXTERNAL_PHY(41)
- EXTERNAL_PHY(42)
- EXTERNAL_PHY(43)
- EXTERNAL_PHY(44)
- EXTERNAL_PHY(45)
- EXTERNAL_PHY(46)
- EXTERNAL_PHY(47)
-
- /* RTL8393 Internal SerDes */
- INTERNAL_PHY(48)
- INTERNAL_PHY(49)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, qsgmii)
- SWITCH_PORT(9, 10, qsgmii)
- SWITCH_PORT(10, 11, qsgmii)
- SWITCH_PORT(11, 12, qsgmii)
- SWITCH_PORT(12, 13, qsgmii)
- SWITCH_PORT(13, 14, qsgmii)
- SWITCH_PORT(14, 15, qsgmii)
- SWITCH_PORT(15, 16, qsgmii)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- SWITCH_PORT(24, 25, qsgmii)
- SWITCH_PORT(25, 26, qsgmii)
- SWITCH_PORT(26, 27, qsgmii)
- SWITCH_PORT(27, 28, qsgmii)
- SWITCH_PORT(28, 29, qsgmii)
- SWITCH_PORT(29, 30, qsgmii)
- SWITCH_PORT(30, 31, qsgmii)
- SWITCH_PORT(31, 32, qsgmii)
-
- SWITCH_PORT(32, 33, qsgmii)
- SWITCH_PORT(33, 34, qsgmii)
- SWITCH_PORT(34, 35, qsgmii)
- SWITCH_PORT(35, 36, qsgmii)
- SWITCH_PORT(36, 37, qsgmii)
- SWITCH_PORT(37, 38, qsgmii)
- SWITCH_PORT(38, 39, qsgmii)
- SWITCH_PORT(39, 40, qsgmii)
-
- SWITCH_PORT(40, 41, qsgmii)
- SWITCH_PORT(41, 42, qsgmii)
- SWITCH_PORT(42, 43, qsgmii)
- SWITCH_PORT(43, 44, qsgmii)
- SWITCH_PORT(44, 45, qsgmii)
- SWITCH_PORT(45, 46, qsgmii)
- SWITCH_PORT(46, 47, qsgmii)
- SWITCH_PORT(47, 48, qsgmii)
-
- /* SFP cages */
- SWITCH_SFP_PORT(48, 49, sgmii)
- SWITCH_SFP_PORT(49, 50, sgmii)
-
- /* CPU-Port */
- port@52 {
- ethernet = <ðernet0>;
- reg = <52>;
- phy-mode = "qsgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl839x.dtsi"
-#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
-
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- compatible = "panasonic,m48eg-pn28480k", "realtek,rtl8393-soc";
- model = "Panasonic Switch-M48eG PN28480K";
-
- aliases {
- led-boot = &led_status_eco_green;
- led-failsafe = &led_status_eco_amber;
- led-running = &led_status_eco_green;
- led-upgrade = &led_status_eco_green;
- };
-
- fan: gpio-fan {
- compatible = "gpio-fan";
- gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
- /* the actual speeds (rpm) are unknown, just use dummy values */
- gpio-fan,speed-map = <1 0>, <2 1>;
- #cooling-cells = <2>;
- };
-
- /*
- * sfp0/1/2/3 are "combo" port with each TP port (45/46/47/48),
- * and they are connected to the RTL8218FB. Currently, there is
- * no support for the chip and only TP ports work by the RTL8218B
- * support.
- */
- sfp0: sfp-p45 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- };
-
- sfp1: sfp-p46 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
-
- sfp2: sfp-p47 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c2>;
- tx-fault-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- };
-
- sfp3: sfp-p48 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c3>;
- tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
- tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
- los-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
- };
-
- thermal-zones {
- /*
- * Zone for SoC temperature
- *
- * Fan speed:
- *
- * - 0-44 celsius: Low
- * - 45-54 celsius: High
- */
- cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <2000>;
-
- thermal-sensors = <&tsens_soc>;
-
- trips {
- cpu_alert: trip-point {
- temperature = <45000>;
- hysteresis = <4000>;
- type = "active";
- };
-
- cpu_crit {
- temperature = <55000>;
- hysteresis = <1000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map {
- trip = <&cpu_alert>;
- cooling-device = <&fan 0 1>;
- };
- };
- };
-
- /*
- * Zone for system temperature
- *
- * Fan speed:
- *
- * - 0-39 celsius: Low
- * - 40-49 celsius: High
- *
- * Note: official recommended ranges of temperature on each
- * fan speed setting:
- *
- * - Low speed : 0-40 celsius
- * - High speed: 0-50 celsius
- *
- * (stock firmware doesn't support auto-selection of
- * speed and need to be selected manually by user)
- */
- sys-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <2000>;
-
- thermal-sensors = <&tsens_sys>;
-
- trips {
- sys_alert: trip-point {
- temperature = <40000>;
- hysteresis = <4000>;
- type = "active";
- };
-
- sys_crit {
- temperature = <50000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map {
- trip = <&sys_alert>;
- cooling-device = <&fan 0 1>;
- };
- };
- };
- };
-};
-
-&leds {
- led_status_eco_amber: led-5 {
- label = "amber:status_eco";
- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_STATUS;
- function-enumerator = <1>;
- };
-
- led_status_eco_green: led-6 {
- label = "green:status_eco";
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- function-enumerator = <2>;
- };
-};
-
-&i2c_gpio_0 {
- scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-
- /* Microchip TCN75A (for SoC) */
- tsens_soc: sensor@48 {
- compatible = "microchip,tcn75";
- reg = <0x48>;
- #thermal-sensor-cells = <0>;
- };
-
- /* Microchip TCN75A (for System) */
- tsens_sys: sensor@49 {
- compatible = "microchip,tcn75";
- reg = <0x49>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&i2c_gpio_1 {
- scl-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
-};
-
-&gpio2 {
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&gpio0>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
-
- /*
- * GPIO12 (IO1_4): 5x RTL8218B + RTL8218FB
- *
- * This GPIO pin should be specified as "reset-gpio" in mdio node,
- * but the current configuration of RTL8218B phy in the phy driver
- * seems to be incomplete and RTL8218FB phy won't be configured on
- * RTL8218D support. So, ethernet ports on these phys will be broken
- * after hard-resetting.
- * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
- * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
- * by resetting.
- */
- ext_switch_reset {
- gpio-hog;
- gpios = <12 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "ext-switch-reset";
- };
-};
-
-&i2c_switch {
- i2c0: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- };
-
- i2c1: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- };
-
- i2c2: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- };
-
- i2c3: i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- };
-};
-
-ðernet0 {
- mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- EXTERNAL_PHY(8)
- EXTERNAL_PHY(9)
- EXTERNAL_PHY(10)
- EXTERNAL_PHY(11)
- EXTERNAL_PHY(12)
- EXTERNAL_PHY(13)
- EXTERNAL_PHY(14)
- EXTERNAL_PHY(15)
-
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- EXTERNAL_PHY(24)
- EXTERNAL_PHY(25)
- EXTERNAL_PHY(26)
- EXTERNAL_PHY(27)
- EXTERNAL_PHY(28)
- EXTERNAL_PHY(29)
- EXTERNAL_PHY(30)
- EXTERNAL_PHY(31)
-
- EXTERNAL_PHY(32)
- EXTERNAL_PHY(33)
- EXTERNAL_PHY(34)
- EXTERNAL_PHY(35)
- EXTERNAL_PHY(36)
- EXTERNAL_PHY(37)
- EXTERNAL_PHY(38)
- EXTERNAL_PHY(39)
-
- /* RTL8218FB */
- EXTERNAL_PHY(40)
- EXTERNAL_PHY(41)
- EXTERNAL_PHY(42)
- EXTERNAL_PHY(43)
- EXTERNAL_PHY(44)
- EXTERNAL_PHY(45)
- EXTERNAL_PHY(46)
- EXTERNAL_PHY(47)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 1, qsgmii)
- SWITCH_PORT(1, 2, qsgmii)
- SWITCH_PORT(2, 3, qsgmii)
- SWITCH_PORT(3, 4, qsgmii)
- SWITCH_PORT(4, 5, qsgmii)
- SWITCH_PORT(5, 6, qsgmii)
- SWITCH_PORT(6, 7, qsgmii)
- SWITCH_PORT(7, 8, qsgmii)
-
- SWITCH_PORT(8, 9, qsgmii)
- SWITCH_PORT(9, 10, qsgmii)
- SWITCH_PORT(10, 11, qsgmii)
- SWITCH_PORT(11, 12, qsgmii)
- SWITCH_PORT(12, 13, qsgmii)
- SWITCH_PORT(13, 14, qsgmii)
- SWITCH_PORT(14, 15, qsgmii)
- SWITCH_PORT(15, 16, qsgmii)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- SWITCH_PORT(24, 25, qsgmii)
- SWITCH_PORT(25, 26, qsgmii)
- SWITCH_PORT(26, 27, qsgmii)
- SWITCH_PORT(27, 28, qsgmii)
- SWITCH_PORT(28, 29, qsgmii)
- SWITCH_PORT(29, 30, qsgmii)
- SWITCH_PORT(30, 31, qsgmii)
- SWITCH_PORT(31, 32, qsgmii)
-
- SWITCH_PORT(32, 33, qsgmii)
- SWITCH_PORT(33, 34, qsgmii)
- SWITCH_PORT(34, 35, qsgmii)
- SWITCH_PORT(35, 36, qsgmii)
- SWITCH_PORT(36, 37, qsgmii)
- SWITCH_PORT(37, 38, qsgmii)
- SWITCH_PORT(38, 39, qsgmii)
- SWITCH_PORT(39, 40, qsgmii)
-
- SWITCH_PORT(40, 41, qsgmii)
- SWITCH_PORT(41, 42, qsgmii)
- SWITCH_PORT(42, 43, qsgmii)
- SWITCH_PORT(43, 44, qsgmii)
- SWITCH_PORT(44, 45, qsgmii)
- SWITCH_PORT(45, 46, qsgmii)
- SWITCH_PORT(46, 47, qsgmii)
- SWITCH_PORT(47, 48, qsgmii)
-
- port@52 {
- ethernet = <ðernet0>;
- reg = <52>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "rtl839x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "tplink,sg2452p-v4", "realtek,rtl8393-soc";
- model = "TP-Link SG2452P v4";
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x10000000>;
- };
-
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- label-mac-device = ðernet0;
- };
-
- chosen {
- stdout-path = "serial0:38400n8";
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- speed {
- label = "speed";
- gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
- };
-
- gpio_fan_sys {
- compatible = "gpio-fan";
- alarm-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
- };
-
- gpio_fan_psu_1 {
- pinctrl-names = "default";
- pinctrl-0 = <&disable_jtag>;
- compatible = "gpio-fan";
-
- alarm-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
- /* the actual speeds (rpm) are unknown, just use dummy values */
- gpio-fan,speed-map = <1 0>, <2 1>;
- #cooling-cells = <2>;
- };
-
- gpio_fan_psu_2 {
- /* This fan runs in parallel to PSU1 fan, but has a separate
- * alarm GPIO. This is not (yet) supported by the gpio-fan driver,
- * so a separate instance is added
- */
- compatible = "gpio-fan";
- alarm-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
- };
-
- leds {
- pinctrl-names = "default";
- compatible = "gpio-leds";
-
- led-0 {
- label = "green:speed";
- gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- };
-
- led-1 {
- label = "green:poe";
- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- };
-
- led_sys: led-2 {
- label = "green:sys";
- gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- };
-
- led-3 {
- label = "green:fan";
- gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- };
-
- led-4 {
- label = "amber:fan";
- gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- function = "fault-fan";
- };
-
- led-5 {
- label = "green:poe-max";
- gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = "alarm-poe";
- };
- };
-
- i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* LAN9 - LAN12 */
- tps23861@5 {
- compatible = "ti,tps23861";
- reg = <0x05>;
- };
-
- /* LAN17 - LAN20 */
- tps23861@6 {
- compatible = "ti,tps23861";
- reg = <0x06>;
- };
-
- /* LAN45 - LAN48 */
- tps23861@9 {
- compatible = "ti,tps23861";
- reg = <0x09>;
- };
-
- /* LAN37 - LAN40 */
- tps23861@a {
- compatible = "ti,tps23861";
- reg = <0x0a>;
- };
-
- /* LAN1 - LAN4 */
- tps23861@14 {
- compatible = "ti,tps23861";
- reg = <0x14>;
- };
-
- /* LAN25 - LAN28 */
- tps23861@24 {
- compatible = "ti,tps23861";
- reg = <0x24>;
- };
-
- /* LAN33 - LAN 36 */
- tps23861@25 {
- compatible = "ti,tps23861";
- reg = <0x25>;
- };
-
- /* LAN41 - LAN44 */
- tps23861@26 {
- compatible = "ti,tps23861";
- reg = <0x26>;
- };
-
- /* LAN13 - LAN16 */
- tps23861@29 {
- compatible = "ti,tps23861";
- reg = <0x29>;
- };
-
- /* LAN29 - LAN32 */
- tps23861@2c {
- compatible = "ti,tps23861";
- reg = <0x2c>;
- };
-
- /* LAN5 - LAN8 */
- tps23861@48 {
- compatible = "ti,tps23861";
- reg = <0x48>;
- };
-
- /* LAN21 - LAN24 */
- tps23861@49 {
- compatible = "ti,tps23861";
- reg = <0x49>;
- };
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
- };
-};
-
-&gpio0 {
- poe-enable {
- gpio-hog;
- gpios = <23 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "poe-enable";
- };
-};
-
-&spi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0xe0000>;
- read-only;
- };
- partition@e0000 {
- label = "u-boot-env";
- reg = <0xe0000 0x20000>;
- };
-
- /* We use the "sys", "usrimg1" and "usrimg2" partitions
- * as firmware since the kernel needs to be in "sys", but the
- * partition is too small to hold the "rootfs" as well.
- * The original partition map contains:
- *
- * partition@100000 {
- * label = "sys";
- * reg = <0x100000 0x600000>;
- * };
- * partition@700000 {
- * label = "usrimg1";
- * reg = <0x700000 0xa00000>;
- * };
- * partition@1100000 {
- * label = "usrimg2";
- * reg = <0x1100000 0xa00000>;
- * };
- */
-
- partition@100000 {
- label = "firmware";
- reg = <0x100000 0x1a00000>;
- };
- partition@1b00000 {
- label = "usrappfs";
- reg = <0x1b00000 0x400000>;
- };
- partition@1f00000 {
- label = "para";
- reg = <0x1f00000 0x100000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- factory_macaddr: macaddr@fdff4 {
- reg = <0xfdff4 0x6>;
- };
- };
- };
- };
- };
-};
-
-ðernet0 {
- nvmem-cells = <&factory_macaddr>;
- nvmem-cell-names = "mac-address";
-
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* External phy RTL8218B #1 */
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- /* External phy RTL8218B #2 */
- EXTERNAL_PHY(8)
- EXTERNAL_PHY(9)
- EXTERNAL_PHY(10)
- EXTERNAL_PHY(11)
- EXTERNAL_PHY(12)
- EXTERNAL_PHY(13)
- EXTERNAL_PHY(14)
- EXTERNAL_PHY(15)
-
- /* External phy RTL8218B #3 */
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- /* External phy RTL8218B #4 */
- EXTERNAL_PHY(24)
- EXTERNAL_PHY(25)
- EXTERNAL_PHY(26)
- EXTERNAL_PHY(27)
- EXTERNAL_PHY(28)
- EXTERNAL_PHY(29)
- EXTERNAL_PHY(30)
- EXTERNAL_PHY(31)
-
- /* External phy RTL8218B #5 */
- EXTERNAL_PHY(32)
- EXTERNAL_PHY(33)
- EXTERNAL_PHY(34)
- EXTERNAL_PHY(35)
- EXTERNAL_PHY(36)
- EXTERNAL_PHY(37)
- EXTERNAL_PHY(38)
- EXTERNAL_PHY(39)
-
- /* External phy RTL8218B #6 */
- EXTERNAL_PHY(40)
- EXTERNAL_PHY(41)
- EXTERNAL_PHY(42)
- EXTERNAL_PHY(43)
- EXTERNAL_PHY(44)
- EXTERNAL_PHY(45)
- EXTERNAL_PHY(46)
- EXTERNAL_PHY(47)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 01, qsgmii)
- SWITCH_PORT(1, 02, qsgmii)
- SWITCH_PORT(2, 03, qsgmii)
- SWITCH_PORT(3, 04, qsgmii)
- SWITCH_PORT(4, 05, qsgmii)
- SWITCH_PORT(5, 06, qsgmii)
- SWITCH_PORT(6, 07, qsgmii)
- SWITCH_PORT(7, 08, qsgmii)
-
- SWITCH_PORT(8, 09, qsgmii)
- SWITCH_PORT(9, 10, qsgmii)
- SWITCH_PORT(10, 11, qsgmii)
- SWITCH_PORT(11, 12, qsgmii)
- SWITCH_PORT(12, 13, qsgmii)
- SWITCH_PORT(13, 14, qsgmii)
- SWITCH_PORT(14, 15, qsgmii)
- SWITCH_PORT(15, 16, qsgmii)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- SWITCH_PORT(24, 25, qsgmii)
- SWITCH_PORT(25, 26, qsgmii)
- SWITCH_PORT(26, 27, qsgmii)
- SWITCH_PORT(27, 28, qsgmii)
- SWITCH_PORT(28, 29, qsgmii)
- SWITCH_PORT(29, 30, qsgmii)
- SWITCH_PORT(30, 31, qsgmii)
- SWITCH_PORT(31, 32, qsgmii)
-
- SWITCH_PORT(32, 33, qsgmii)
- SWITCH_PORT(33, 34, qsgmii)
- SWITCH_PORT(34, 35, qsgmii)
- SWITCH_PORT(35, 36, qsgmii)
- SWITCH_PORT(36, 37, qsgmii)
- SWITCH_PORT(37, 38, qsgmii)
- SWITCH_PORT(38, 39, qsgmii)
- SWITCH_PORT(39, 40, qsgmii)
-
- SWITCH_PORT(40, 41, qsgmii)
- SWITCH_PORT(41, 42, qsgmii)
- SWITCH_PORT(42, 43, qsgmii)
- SWITCH_PORT(43, 44, qsgmii)
- SWITCH_PORT(44, 45, qsgmii)
- SWITCH_PORT(45, 46, qsgmii)
- SWITCH_PORT(46, 47, qsgmii)
- SWITCH_PORT(47, 48, qsgmii)
-
- /* CPU-Port */
- port@52 {
- ethernet = <ðernet0>;
- reg = <52>;
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-/dts-v1/;
-
-#include "rtl839x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- compatible = "zyxel,gs1900-48", "realtek,rtl8393-soc";
- model = "Zyxel GS1900-48";
-
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- leds {
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
- compatible = "gpio-leds";
-
- led_sys: sys {
- label = "green:sys";
- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- indirect-access-bus-id = <3>;
- gpio-controller;
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
- };
-
- keys {
- compatible = "gpio-keys-polled";
- poll-interval = <20>;
-
- mode {
- label = "reset";
- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- /* i2c of the left SFP cage: port 49 */
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-p9 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
- };
-
- /* i2c of the right SFP cage: port 50 */
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-p10 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&spi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "u-boot-env";
- reg = <0x40000 0x10000>;
- read-only;
- };
- partition@50000 {
- label = "u-boot-env2";
- reg = <0x50000 0x10000>;
- read-only;
- };
- partition@60000 {
- label = "jffs";
- reg = <0x60000 0x100000>;
- };
- partition@160000 {
- label = "jffs2";
- reg = <0x160000 0x100000>;
- };
- partition@260000 {
- label = "firmware";
- reg = <0x260000 0x6d0000>;
- compatible = "openwrt,uimage", "denx,uimage";
- openwrt,ih-magic = <0x83800000>;
- };
- partition@930000 {
- label = "runtime2";
- reg = <0x930000 0x6d0000>;
- };
- };
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* External phy RTL8218B #1 */
- EXTERNAL_PHY(0)
- EXTERNAL_PHY(1)
- EXTERNAL_PHY(2)
- EXTERNAL_PHY(3)
- EXTERNAL_PHY(4)
- EXTERNAL_PHY(5)
- EXTERNAL_PHY(6)
- EXTERNAL_PHY(7)
-
- /* External phy RTL8218B #2 */
- EXTERNAL_PHY(8)
- EXTERNAL_PHY(9)
- EXTERNAL_PHY(10)
- EXTERNAL_PHY(11)
- EXTERNAL_PHY(12)
- EXTERNAL_PHY(13)
- EXTERNAL_PHY(14)
- EXTERNAL_PHY(15)
-
- /* External phy RTL8218B #3 */
- EXTERNAL_PHY(16)
- EXTERNAL_PHY(17)
- EXTERNAL_PHY(18)
- EXTERNAL_PHY(19)
- EXTERNAL_PHY(20)
- EXTERNAL_PHY(21)
- EXTERNAL_PHY(22)
- EXTERNAL_PHY(23)
-
- /* External phy RTL8218B #4 */
- EXTERNAL_PHY(24)
- EXTERNAL_PHY(25)
- EXTERNAL_PHY(26)
- EXTERNAL_PHY(27)
- EXTERNAL_PHY(28)
- EXTERNAL_PHY(29)
- EXTERNAL_PHY(30)
- EXTERNAL_PHY(31)
-
- /* External phy RTL8218B #5 */
- EXTERNAL_PHY(32)
- EXTERNAL_PHY(33)
- EXTERNAL_PHY(34)
- EXTERNAL_PHY(35)
- EXTERNAL_PHY(36)
- EXTERNAL_PHY(37)
- EXTERNAL_PHY(38)
- EXTERNAL_PHY(39)
-
- /* External phy RTL8218B #6 */
- EXTERNAL_PHY(40)
- EXTERNAL_PHY(41)
- EXTERNAL_PHY(42)
- EXTERNAL_PHY(43)
- EXTERNAL_PHY(44)
- EXTERNAL_PHY(45)
- EXTERNAL_PHY(46)
- EXTERNAL_PHY(47)
-
- /* RTL8393 Internal SerDes */
- INTERNAL_PHY(48)
- INTERNAL_PHY(49)
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- SWITCH_PORT(0, 01, qsgmii)
- SWITCH_PORT(1, 02, qsgmii)
- SWITCH_PORT(2, 03, qsgmii)
- SWITCH_PORT(3, 04, qsgmii)
- SWITCH_PORT(4, 05, qsgmii)
- SWITCH_PORT(5, 06, qsgmii)
- SWITCH_PORT(6, 07, qsgmii)
- SWITCH_PORT(7, 08, qsgmii)
-
- SWITCH_PORT(8, 09, qsgmii)
- SWITCH_PORT(9, 10, qsgmii)
- SWITCH_PORT(10, 11, qsgmii)
- SWITCH_PORT(11, 12, qsgmii)
- SWITCH_PORT(12, 13, qsgmii)
- SWITCH_PORT(13, 14, qsgmii)
- SWITCH_PORT(14, 15, qsgmii)
- SWITCH_PORT(15, 16, qsgmii)
-
- SWITCH_PORT(16, 17, qsgmii)
- SWITCH_PORT(17, 18, qsgmii)
- SWITCH_PORT(18, 19, qsgmii)
- SWITCH_PORT(19, 20, qsgmii)
- SWITCH_PORT(20, 21, qsgmii)
- SWITCH_PORT(21, 22, qsgmii)
- SWITCH_PORT(22, 23, qsgmii)
- SWITCH_PORT(23, 24, qsgmii)
-
- SWITCH_PORT(24, 25, qsgmii)
- SWITCH_PORT(25, 26, qsgmii)
- SWITCH_PORT(26, 27, qsgmii)
- SWITCH_PORT(27, 28, qsgmii)
- SWITCH_PORT(28, 29, qsgmii)
- SWITCH_PORT(29, 30, qsgmii)
- SWITCH_PORT(30, 31, qsgmii)
- SWITCH_PORT(31, 32, qsgmii)
-
- SWITCH_PORT(32, 33, qsgmii)
- SWITCH_PORT(33, 34, qsgmii)
- SWITCH_PORT(34, 35, qsgmii)
- SWITCH_PORT(35, 36, qsgmii)
- SWITCH_PORT(36, 37, qsgmii)
- SWITCH_PORT(37, 38, qsgmii)
- SWITCH_PORT(38, 39, qsgmii)
- SWITCH_PORT(39, 40, qsgmii)
-
- SWITCH_PORT(40, 41, qsgmii)
- SWITCH_PORT(41, 42, qsgmii)
- SWITCH_PORT(42, 43, qsgmii)
- SWITCH_PORT(43, 44, qsgmii)
- SWITCH_PORT(44, 45, qsgmii)
- SWITCH_PORT(45, 46, qsgmii)
- SWITCH_PORT(46, 47, qsgmii)
- SWITCH_PORT(47, 48, qsgmii)
-
- /* SFP cages */
- port@48 {
- reg = <48>;
- label = "lan49";
- phy-mode = "sgmii";
- phy-handle = <&phy48>;
- sfp = <&sfp0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
-
- };
-
- port@49 {
- reg = <49>;
- label = "lan50";
- phy-mode = "sgmii";
- phy-handle = <&phy49>;
- sfp = <&sfp1>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
-
- };
-
- /* CPU-Port */
- port@52 {
- ethernet = <ðernet0>;
- reg = <52>;
- phy-mode = "qsgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/clock/rtl83xx-clk.h>
-
-/dts-v1/;
-
-#define STRINGIZE(s) #s
-#define LAN_LABEL(p, s) STRINGIZE(p ## s)
-#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
-
-#define INTERNAL_PHY(n) \
- phy##n: ethernet-phy@##n { \
- reg = <##n>; \
- compatible = "ethernet-phy-ieee802.3-c22"; \
- phy-is-integrated; \
- };
-
-#define EXTERNAL_PHY(n) \
- phy##n: ethernet-phy@##n { \
- reg = <##n>; \
- compatible = "ethernet-phy-ieee802.3-c22"; \
- };
-
-#define EXTERNAL_SFP_PHY(n) \
- phy##n: ethernet-phy@##n { \
- compatible = "ethernet-phy-ieee802.3-c22"; \
- sfp; \
- media = "fibre"; \
- reg = <##n>; \
- };
-
-#define EXTERNAL_SFP_PHY_FULL(n, s) \
- phy##n: ethernet-phy@##n { \
- compatible = "ethernet-phy-ieee802.3-c22"; \
- sfp = <&sfp##s>; \
- reg = <##n>; \
- };
-
-#define SWITCH_PORT(n, s, m) \
- port@##n { \
- reg = <##n>; \
- label = SWITCH_PORT_LABEL(s) ; \
- phy-handle = <&phy##n>; \
- phy-mode = #m ; \
- };
-
-#define SWITCH_SFP_PORT(n, s, m) \
- port@##n { \
- reg = <##n>; \
- label = SWITCH_PORT_LABEL(s) ; \
- phy-handle = <&phy##n>; \
- phy-mode = #m ; \
- fixed-link { \
- speed = <1000>; \
- full-duplex; \
- }; \
- };
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- compatible = "realtek,rtl839x-soc";
-
- osc: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- };
-
- ccu: clock-controller {
- compatible = "realtek,rtl8390-clock";
- #clock-cells = <1>;
- clocks = <&osc>;
- clock-names = "ref_clk";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "mips,mips34Kc";
- reg = <0>;
- clocks = <&ccu CLK_CPU>;
- operating-points-v2 = <&cpu_opp_table>;
- };
-
- cpu@1 {
- compatible = "mips,mips34Kc";
- reg = <1>;
- clocks = <&ccu CLK_CPU>;
- operating-points-v2 = <&cpu_opp_table>;
- };
- };
-
- cpu_opp_table: opp-table-0 {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp00 {
- opp-hz = /bits/ 64 <425000000>;
- };
- opp01 {
- opp-hz = /bits/ 64 <450000000>;
- };
- opp02 {
- opp-hz = /bits/ 64 <475000000>;
- };
- opp03 {
- opp-hz = /bits/ 64 <500000000>;
- };
- opp04 {
- opp-hz = /bits/ 64 <525000000>;
- };
- opp05 {
- opp-hz = /bits/ 64 <550000000>;
- };
- opp06 {
- opp-hz = /bits/ 64 <575000000>;
- };
- opp07 {
- opp-hz = /bits/ 64 <600000000>;
- };
- opp08 {
- opp-hz = /bits/ 64 <625000000>;
- };
- opp09 {
- opp-hz = /bits/ 64 <650000000>;
- };
- opp10 {
- opp-hz = /bits/ 64 <675000000>;
- };
- opp11 {
- opp-hz = /bits/ 64 <700000000>;
- };
- opp12 {
- opp-hz = /bits/ 64 <725000000>;
- };
- opp13 {
- opp-hz = /bits/ 64 <750000000>;
- };
- };
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- };
-
- cpuintc: cpuintc {
- compatible = "mti,cpu-interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x18000000 0x10000>;
-
- intc: interrupt-controller@3000 {
- compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
- reg = <0x3000 0x18>, <0x3018 0x18>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&cpuintc>;
- interrupts = <2>, <3>, <4>, <5>, <6>;
- };
-
- spi0: spi@1200 {
- compatible = "realtek,rtl8380-spi";
- reg = <0x1200 0x100>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- timer0: timer@3100 {
- compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
- reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
- <0x3130 0x10>, <0x3140 0x10>;
-
- interrupt-parent = <&intc>;
- interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
- clocks = <&ccu CLK_LXB>;
- };
-
- uart0: uart@2000 {
- compatible = "ns16550a";
- reg = <0x2000 0x100>;
-
- clocks = <&ccu CLK_LXB>;
-
- interrupt-parent = <&intc>;
- interrupts = <31 1>;
-
- reg-io-width = <1>;
- reg-shift = <2>;
- fifo-size = <1>;
- no-loopback-test;
- };
-
- uart1: uart@2100 {
- pinctrl-names = "default";
- pinctrl-0 = <&enable_uart1>;
-
- compatible = "ns16550a";
- reg = <0x2100 0x100>;
-
- clocks = <&ccu CLK_LXB>;
-
- interrupt-parent = <&intc>;
- interrupts = <30 2>;
-
- reg-io-width = <1>;
- reg-shift = <2>;
- fifo-size = <1>;
- no-loopback-test;
-
- status = "disabled";
- };
-
- gpio0: gpio-controller@3500 {
- compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
- reg = <0x3500 0x20>;
-
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <24>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupts = <23 2>;
- };
-
- watchdog0: watchdog@3150 {
- compatible = "realtek,rtl8390-wdt";
- reg = <0x3150 0xc>;
-
- realtek,reset-mode = "soc";
-
- clocks = <&ccu CLK_LXB>;
- timeout-sec = <30>;
-
- interrupt-parent = <&intc>;
- interrupt-names = "phase1", "phase2";
- interrupts = <19 4>, <18 4>;
- };
-
- };
-
- pinmux@1b000004 {
- compatible = "pinctrl-single";
- reg = <0x1b000004 0x4>;
-
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x1>;
- #pinctrl-cells = <2>;
-
- enable_uart1: pinmux_enable_uart1 {
- pinctrl-single,bits = <0x0 0x1 0x3>;
- };
-
- disable_jtag: pinmux_disable_jtag {
- pinctrl-single,bits = <0x0 0x2 0x3>;
- };
- };
-
- /* LED_GLB_CTRL */
- pinmux@1b0000e4 {
- compatible = "pinctrl-single";
- reg = <0x1b0000e4 0x4>;
-
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x1>;
- #pinctrl-cells = <2>;
-
- /* enable GPIO 0 */
- pinmux_disable_sys_led: disable_sys_led {
- pinctrl-single,bits = <0x0 0x0 0x4000>;
- };
- };
-
- ethernet0: ethernet@1b00a300 {
- compatible = "realtek,rtl838x-eth";
- reg = <0x1b00a300 0x100>;
-
- interrupt-parent = <&intc>;
- interrupts = <24 3>;
-
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- sram0: sram@9f000000 {
- compatible = "mmio-sram";
- reg = <0x9f000000 0x18000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x9f000000 0x18000>;
- };
-
- switch0: switch@1b000000 {
- status = "okay";
- compatible = "realtek,rtl83xx-switch";
-
- interrupt-parent = <&intc>;
- interrupts = <20 2>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/ {
- /* Lan 49 */
- i2c0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp0: sfp-p49 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
- /* tx-disable-gpio handled by RTL8214FC based on media setting */
- };
-
- /* Lan 50 */
- i2c1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp1: sfp-p50 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c1>;
- los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- /* tx-disable-gpio handled by RTL8214FC based on media setting */
- };
-
- /* Lan 51 */
- i2c2: i2c-gpio-2 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp2: sfp-p51 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c2>;
- los-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>;
- /* tx-disable-gpio handled by RTL8214FC based on media setting */
- };
-
- /* Lan 52 */
- i2c3: i2c-gpio-3 {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- sfp3: sfp-p52 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c3>;
- los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
- /* tx-disable-gpio handled by RTL8214FC based on media setting */
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- leds: leds {
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
- compatible = "gpio-leds";
-
- led_power: power {
- label = "green:power";
- gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&gpio0 {
- indirect-access-bus-id = <0>;
-};
-
-&spi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x00000000 0x80000>;
- read-only;
- };
- partition@80000 {
- label = "u-boot-env";
- reg = <0x00080000 0x40000>;
- };
- partition@c0000 {
- label = "board-name";
- reg = <0x000c0000 0x40000>;
- };
- partition@280000 {
- label = "firmware";
- compatible = "denx,uimage";
- reg = <0x00100000 0xd80000>;
- };
- partition@be80000 {
- label = "kernel2";
- reg = <0x00e80000 0x180000>;
- };
- partition@1000000 {
- label = "sysinfo";
- reg = <0x01000000 0x40000>;
- };
- partition@1040000 {
- label = "rootfs2";
- reg = <0x01040000 0xc00000>;
- };
- partition@1c40000 {
- label = "jffs2";
- reg = <0x01c40000 0x3c0000>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/ {
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
- open-source;
- };
-
- keys: keys {
- compatible = "gpio-keys-polled";
- poll-interval = <20>;
-
- reset {
- label = "reset";
- gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- gpio1: rtl8231-gpio {
- compatible = "realtek,rtl8231-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- indirect-access-bus-id = <0>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- chosen {
- stdout-path = "serial0:9600n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- leds: leds {
- compatible = "gpio-leds";
-
- led-0 {
- label = "amber:any_col";
- gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_FAULT;
- };
-
- led-1 {
- label = "green:giga";
- gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <1>;
- };
-
- led-2 {
- label = "green:100m";
- gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <2>;
- };
-
- led-3 {
- label = "green:full";
- gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <3>;
- };
-
- led-4 {
- label = "green:loop_history";
- gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- function-enumerator = <4>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- led_mode {
- label = "led-mode";
- gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- };
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
- };
-
- i2c_gpio_0: i2c-gpio-0 {
- compatible = "i2c-gpio";
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio1: gpio@20 {
- compatible = "nxp,pca9555";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio2: gpio@75 {
- compatible = "nxp,pca9539";
- reg = <0x75>;
- gpio-controller;
- #gpio-cells = <2>;
-
- /*
- * GPIO14 (IO1_6): Shift Register RESET (port LED)
- * - Switch-M8eG PN28080K: 3x 74HC164
- * - Switch-M16eG PN28160K: 4x 74HC164
- * - Switch-M24eG PN28240K: 6x 74HC164
- * - Switch-M48eG PN28480K: 12x 74HC164
- */
- portled_sregister_reset {
- gpio-hog;
- gpios = <14 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "portled-sregister-reset";
- };
- };
- };
-
- i2c_gpio_1: i2c-gpio-1 {
- compatible = "i2c-gpio";
- i2c-gpio,delay-us = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c_switch: i2c-switch@70 {
- compatible = "nxp,pca9545";
- reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-&spi0 {
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "u-boot-env";
- reg = <0x80000 0x10000>;
- };
-
- partition@90000 {
- label = "u-boot-env2";
- reg = <0x90000 0x10000>;
- };
-
- partition@a0000 {
- label = "sysinfo";
- reg = <0xa0000 0x60000>;
- read-only;
- };
-
- /*
- * Filesystem area in stock firmware
- * (0x100000-0x1DFFFFF)
- *
- * stock firmware images are required to pass
- * the checking by the U-Boot, also for OpenWrt
- *
- * in OpenWrt:
- * - 0x100000-0xDFFFFF (13M): stock images
- * - 0xE00000-0x1DFFFFF(16M): OpenWrt image
- */
- partition@100000 {
- label = "fs_reserved";
- reg = <0x100000 0xd00000>;
- };
-
- partition@e00000 {
- compatible = "denx,uimage";
- label = "firmware";
- reg = <0xe00000 0x1000000>;
- };
-
- partition@1e00000 {
- label = "vlog_data";
- reg = <0x1e00000 0x100000>;
- read-only;
- };
-
- partition@1f00000 {
- label = "elog_data";
- reg = <0x1f00000 0x100000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-/dts-v1/;
-
-#include "rtl930x.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- compatible = "zyxel,xgs1250-12", "realtek,rtl838x-soc";
- model = "Zyxel XGS1250-12 Switch";
-
- aliases {
- led-boot = &led_pwr_sys;
- led-failsafe = &led_pwr_sys;
- led-running = &led_pwr_sys;
- led-upgrade = &led_pwr_sys;
- };
-
- keys {
- compatible = "gpio-keys";
-
- mode {
- label = "reset";
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- /* i2c of the SFP cage: port 12 */
- i2c0: i2c-rtl9300@1b00036c {
- compatible = "realtek,rtl9300-i2c";
- reg = <0x1b00036c 0x3c>;
- #address-cells = <1>;
- #size-cells = <0>;
- sda-pin = <10>;
- scl-pin = <8>;
- clock-frequency = <100000>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinmux_disable_sys_led>;
-
- led_pwr_sys: led-0 {
- label = "green:power";
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- sfp0: sfp-p12 {
- compatible = "sff,sfp";
- i2c-bus = <&i2c0>;
- los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
- tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
- mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
- tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
- };
-
- led_set: led_set {
- compatible = "realtek,rtl9300-leds";
- active-low;
-
- led_set0 = <0x0a20 0x0b80>; // LED set 0: 1000Mbps, 10/100Mbps
- led_set1 = <0x0a0b 0x0a28 0x0a82 0x0a0b>; // LED set 1: (10G, 5G, 2.5G) (2.5G, 1G)
- // (5G, 10/100) (10G, 5G, 2.5G)
- led_set2 = <0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit
- };
-};
-
-&spi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0 0xe0000>;
- read-only;
- };
- partition@e0000 {
- label = "u-boot-env";
- reg = <0xe0000 0x10000>;
- };
- partition@f0000 {
- label = "u-boot-env2";
- reg = <0xf0000 0x10000>;
- read-only;
- };
- partition@100000 {
- label = "jffs";
- reg = <0x100000 0x100000>;
- };
- partition@200000 {
- label = "jffs2";
- reg = <0x200000 0x100000>;
- };
- partition@b300000 {
- label = "firmware";
- reg = <0x300000 0xce0000>;
- compatible = "openwrt,uimage", "denx,uimage";
- openwrt,ih-magic = <0x93001250>;
- };
- partition@fe0000 {
- label = "log";
- reg = <0xfe0000 0x20000>;
- };
- };
- };
-};
-
-ðernet0 {
- mdio: mdio-bus {
- compatible = "realtek,rtl838x-mdio";
- regmap = <ðernet0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* External RTL8218D PHY */
- phy0: ethernet-phy@0 {
- reg = <0>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 0>;
- sds = < 2 >;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
- phy1: ethernet-phy@1 {
- reg = <1>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 1>;
- };
- phy2: ethernet-phy@2 {
- reg = <2>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 2>;
- };
- phy3: ethernet-phy@3 {
- reg = <3>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 3>;
- };
- phy4: ethernet-phy@4 {
- reg = <4>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 4>;
- };
- phy5: ethernet-phy@5 {
- reg = <5>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 5>;
- };
- phy6: ethernet-phy@6 {
- reg = <6>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 6>;
- };
- phy7: ethernet-phy@7 {
- reg = <7>;
- compatible = "ethernet-phy-ieee802.3-c22";
- rtl9300,smi-address = <0 7>;
- };
-
- /* External Aquantia 113C PHYs */
- phy24: ethernet-phy@24 {
- reg = <24>;
- compatible = "ethernet-phy-ieee802.3-c45";
- rtl9300,smi-address = <1 8>;
- sds = < 6 >;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
- phy25: ethernet-phy@25 {
- reg = <25>;
- compatible = "ethernet-phy-ieee802.3-c45";
- rtl9300,smi-address = <2 8>;
- sds = < 7 >;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
- phy26: ethernet-phy@26 {
- reg = <26>;
- compatible = "ethernet-phy-ieee802.3-c45";
- rtl9300,smi-address = <3 8>;
- sds = < 8 >;
- // Disabled because we do not know how to bring up again
- // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
- /* SFP Ports */
- phy27: ethernet-phy@27 {
- compatible = "ethernet-phy-ieee802.3-c22";
- phy-is-integrated;
- reg = <27>;
- rtl9300,smi-address = <4 0>;
- sds = < 9 >;
- };
-
- };
-};
-
-&switch0 {
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan1";
- phy-handle = <&phy0>;
- phy-mode = "xgmii";
- led-set = <0>;
- };
- port@1 {
- reg = <1>;
- label = "lan2";
- phy-handle = <&phy1>;
- phy-mode = "xgmii";
- led-set = <0>;
- };
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-handle = <&phy2>;
- phy-mode = "xgmii";
- led-set = <0>;
- };
- port@3 {
- reg = <3>;
- label = "lan4";
- phy-handle = <&phy3>;
- phy-mode = "xgmii";
- led-set = <0>;
- };
- port@4 {
- reg = <4>;
- label = "lan5";
- phy-handle = <&phy4>;
- phy-mode = "xgmii";
- led-set = <0>;
- };
- port@5 {
- reg = <5>;
- label = "lan6";
- phy-handle = <&phy5>;
- phy-mode = "xgmii";
- led-set = <0>;
- };
- port@6 {
- reg = <6>;
- label = "lan7";
- phy-handle = <&phy6>;
- phy-mode = "xgmii";
- led-set = <0>;
- };
- port@7 {
- reg = <7>;
- label = "lan8";
- phy-handle = <&phy7>;
- phy-mode = "xgmii";
- led-set = <0>;
- };
-
- port@24 {
- reg = <24>;
- label = "lan9";
- phy-mode = "usxgmii";
- phy-handle = <&phy24>;
- led-set = <1>;
- };
- port@25 {
- reg = <25>;
- label = "lan10";
- phy-mode = "usxgmii";
- phy-handle = <&phy25>;
- led-set = <1>;
- };
- port@26 {
- reg = <26>;
- label = "lan11";
- phy-mode = "usxgmii";
- phy-handle = <&phy26>;
- led-set = <1>;
- };
-
- port@27 {
- reg = <27>;
- label = "lan12";
- phy-mode = "10gbase-r";
- phy-handle = <&phy27>;
- sfp = <&sfp0>;
- led-set = <2>;
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- pause;
- };
-
- };
-
- port@28 {
- ethernet = <ðernet0>;
- reg = <28>;
- phy-mode = "internal";
- fixed-link {
- speed = <10000>;
- full-duplex;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- compatible = "realtek,rtl838x-soc";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- frequency = <800000000>;
-
- cpu@0 {
- compatible = "mips,mips34Kc";
- reg = <0>;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- };
-
- cpuintc: cpuintc {
- compatible = "mti,cpu-interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
-
- lx_clk: lx_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <175000000>;
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x18000000 0x10000>;
-
- intc: interrupt-controller@3000 {
- compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
- reg = <0x3000 0x18>, <0x3018 0x18>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&cpuintc>;
- interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
- };
-
- spi0: spi@1200 {
- compatible = "realtek,rtl8380-spi";
- reg = <0x1200 0x100>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- timer0: timer@3200 {
- compatible = "realtek,rtl930x-timer", "realtek,otto-timer";
- reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
- <0x3230 0x10>, <0x3240 0x10>;
-
- interrupt-parent = <&intc>;
- interrupts = <7 4>, <8 4>, <9 4>, <10 4>, <11 4>;
- clocks = <&lx_clk>;
- };
-
- uart0: uart@2000 {
- compatible = "ns16550a";
- reg = <0x2000 0x100>;
-
- clocks = <&lx_clk>;
-
- interrupt-parent = <&intc>;
- interrupts = <30 1>;
-
- reg-io-width = <1>;
- reg-shift = <2>;
- fifo-size = <1>;
- no-loopback-test;
- };
-
- uart1: uart@2100 {
- compatible = "ns16550a";
- reg = <0x2100 0x100>;
-
- clocks = <&lx_clk>;
-
- interrupt-parent = <&intc>;
- interrupts = <31 0>;
-
- reg-io-width = <1>;
- reg-shift = <2>;
- fifo-size = <1>;
- no-loopback-test;
-
- status = "disabled";
- };
-
- watchdog0: watchdog@3260 {
- compatible = "realtek,rtl9300-wdt";
- reg = <0x3260 0xc>;
-
- realtek,reset-mode = "soc";
-
- clocks = <&lx_clk>;
- timeout-sec = <30>;
-
- interrupt-parent = <&intc>;
- interrupt-names = "phase1", "phase2";
- interrupts = <5 4>, <6 4>;
- };
-
- gpio0: gpio-controller@3300 {
- compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
- reg = <0x3300 0x1c>, <0x3338 0x8>;
-
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <24>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupt-parent = <&intc>;
- interrupts = <13 1>;
- };
-
- };
-
- pinmux_led: pinmux@1b00cc00 {
- compatible = "pinctrl-single";
- reg = <0x1b00cc00 0x4>;
-
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x1>;
- #pinctrl-cells = <2>;
-
- /* enable GPIO 0 */
- pinmux_disable_sys_led: disable_sys_led {
- pinctrl-single,bits = <0x0 0x0 0x1000>;
- };
- };
-
- ethernet0: ethernet@1b00a300 {
- compatible = "realtek,rtl838x-eth";
- reg = <0x1b00a300 0x100>;
-
- interrupt-parent = <&intc>;
- interrupts = <24 3>;
-
- phy-mode = "internal";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- switch0: switch@1b000000 {
- compatible = "realtek,rtl83xx-switch";
- status = "okay";
-
- interrupt-parent = <&intc>;
- interrupts = <23 2>;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/interrupt-controller/mips-gic.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- compatible = "realtek,rtl838x-soc";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- frequency = <1000000000>;
-
- cpu@0 {
- compatible = "mti,interaptive";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "mti,interaptive";
- reg = <1>;
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x10000000>;
- };
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- };
-
- lx_clk: lx_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-
- cpuclock: cpuclock@0 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
-
- /* FIXME: there should be way to detect this */
- clock-frequency = <1000000000>;
- };
-
- cpuintc: cpuintc {
- compatible = "mti,cpu-interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
-
- gic: interrupt-controller@1ddc0000 {
- compatible = "mti,gic";
- reg = <0x1ddc0000 0x20000>;
-
- interrupt-controller;
- #interrupt-cells = <3>;
-
- /*
- * Declare the interrupt-parent even though the mti,gic
- * binding doesn't require it, such that the kernel can
- * figure out that cpu_intc is the root interrupt
- * controller & should be probed first.
- */
- interrupt-parent = <&cpuintc>;
-
- timer {
- compatible = "mti,gic-timer";
- interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
- clocks = <&cpuclock>;
- };
- };
-
- soc: soc {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x18000000 0x10000>;
-
- spi0: spi@1200 {
- status = "okay";
-
- compatible = "realtek,rtl8380-spi";
- reg = <0x1200 0x100>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- watchdog0: watchdog@3260 {
- compatible = "realtek,rtl9310-wdt";
- reg = <0x3260 0xc>;
-
- realtek,reset-mode = "soc";
-
- clocks = <&lx_clk>;
- timeout-sec = <30>;
-
- interrupt-parent = <&gic>;
- interrupt-names = "phase1", "phase2";
- interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 9 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gpio0: gpio-controller@3300 {
- compatible = "realtek,rtl9310-gpio", "realtek,otto-gpio";
- reg = <0x3300 0x1c>;
-
- gpio-controller;
- #gpio-cells = <2>;
- ngpios = <32>;
-
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- uart0: uart@2000 {
- compatible = "ns16550a";
- reg = <0x2000 0x100>;
-
- clock-frequency = <200000000>;
-
- interrupt-parent = <&gic>;
- #interrupt-cells = <3>;
- interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
-
- reg-io-width = <1>;
- reg-shift = <2>;
- fifo-size = <1>;
- no-loopback-test;
- };
-
- uart1: uart@2100 {
- compatible = "ns16550a";
- reg = <0x2100 0x100>;
-
- clock-frequency = <200000000>;
-
- interrupt-parent = <&gic>;
- #interrupt-cells = <3>;
- interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
-
- reg-io-width = <1>;
- reg-shift = <2>;
- fifo-size = <1>;
- no-loopback-test;
-
- status = "disabled";
- };
- };
-
- pinmux: pinmux@1b001358 {
- compatible = "pinctrl-single";
- reg = <0x1b001358 0x4>;
-
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x1>;
- #pinctrl-cells = <2>;
-
- /* Enable GPIO6 and GPIO7, possibly unknown others */
- pinmux_disable_jtag: disable_jtag {
- pinctrl-single,bits = <0x0 0x0 0x8000>;
- };
-
- /* Controls GPIO0 */
- pinmux_disable_sys_led: disable_sys_led {
- pinctrl-single,bits = <0x0 0x0 0x100>;
- };
- };
-
- ethernet0: ethernet@1b00a300 {
- status = "okay";
- compatible = "realtek,rtl838x-eth";
- reg = <0x1b00a300 0x100>;
- interrupt-parent = <&gic>;
- #interrupt-cells = <3>;
- interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
- phy-mode = "internal";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- switch0: switch@1b000000 {
- compatible = "realtek,rtl83xx-switch";
- status = "okay";
-
- interrupt-parent = <&gic>;
- #interrupt-cells = <3>;
- interrupts = <GIC_SHARED 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_d-link_dgs-1210_common.dtsi"
+#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-10mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc";
+
+ model = "D-Link DGS-1210-10MP F";
+
+ /* i2c for sfp port9 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c for sfp port10 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p10 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&leds {
+ link_act {
+ label = "green:link_act";
+ gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ };
+
+ poe {
+ label = "green:poe";
+ gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ };
+
+ poe_max {
+ label = "yellow:poe_max";
+ gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&keys {
+ mode {
+ label = "mode";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_LIGHTS_TOGGLE>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@24 {
+ reg = <24>;
+ label = "lan9";
+ phy-handle = <&phy24>;
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan10";
+ phy-handle = <&phy26>;
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "engenius,ews2910p", "realtek,rtl838x-soc";
+ model = "EnGenius EWS2910P";
+
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_fault;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ led_mode {
+ label = "led-mode";
+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+
+ poe_enable {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "poe-enable";
+ };
+
+ sff_p9_gpios {
+ gpio-hog;
+ gpios = < 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>,
+ < 11 GPIO_ACTIVE_HIGH>, /* los-gpio */
+ < 12 GPIO_ACTIVE_LOW>; /* mod-def0-gpio */
+ input;
+ line-name = "sff-p9-gpios";
+ };
+ };
+
+ gpio-export {
+ compatible = "gpio-export";
+
+ sff-p9-tx-disable {
+ gpio-export,name = "sff-p9-tx-disable";
+ gpio-export,output = <1>;
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: led-0 {
+ label = "green:power";
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ };
+
+ led_lan_mode: led-1 {
+ label = "green:lan-mode";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ };
+
+ led_fault: led-2 {
+ label = "amber:fault";
+ gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ };
+
+ led_poe_max: led-3 {
+ label = "amber:poe-max";
+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ sfp1: sfp-p10 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ read-only;
+ };
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+ partition@a0000 {
+ label = "rootfs_data";
+ reg = <0xa0000 0xd60000>;
+ };
+ partition@e00000 {
+ label = "jffs2-log";
+ reg = <0xe00000 0x200000>;
+ };
+ partition@1000000 {
+ compatible = "openwrt,uimage";
+ label = "firmware";
+ reg = <0x1000000 0x800000>;
+ openwrt,ih-magic = <0x03802910>;
+ };
+ partition@1800000 {
+ label = "firmware2";
+ reg = <0x1800000 0x800000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ SWITCH_SFP_PORT(24, 9, 1000base-x)
+
+ port@26 {
+ reg = <26>;
+ label = "lan10";
+ phy-mode = "1000base-x";
+ phy-handle = <&phy26>;
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8380_hpe_1920-8g.dtsi"
+
+/ {
+ compatible = "hpe,1920-8g-poe-180w", "realtek,rtl838x-soc";
+ model = "HPE 1920-8G-PoE+ 180W (JG922A)";
+};
+
+&uart1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8380_hpe_1920-8g.dtsi"
+
+/ {
+ compatible = "hpe,1920-8g-poe-65w", "realtek,rtl838x-soc";
+ model = "HPE 1920-8G-PoE+ 65W (JG921A)";
+};
+
+&uart1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8380_hpe_1920-8g.dtsi"
+
+/ {
+ compatible = "hpe,1920-8g", "realtek,rtl838x-soc";
+ model = "HPE 1920-8G (JG920A)";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl838x_hpe_1920.dtsi"
+
+/ {
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+ };
+
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ // tx-fault and tx-disable unconnected
+ };
+
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ // tx-fault and tx-disable unconnected
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@24 {
+ reg = <24>;
+ label = "lan9";
+ phy-handle = <&phy24>;
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan10";
+ phy-handle = <&phy26>;
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "realtek,rtl838x-soc";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+
+ compatible = "gpio-keys";
+
+ mode {
+ label = "reset";
+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+ open-source;
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <31>;
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x00e0000>;
+ read-only;
+ };
+
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0x00e0000 0x0010000>;
+ };
+
+ partition@f0000 {
+ label = "u-boot-env2";
+ reg = <0x00f0000 0x0010000>;
+ };
+
+ partition@100000 {
+ label = "jffs";
+ reg = <0x0100000 0x0100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "jffs2";
+ reg = <0x0200000 0x0100000>;
+ read-only;
+ };
+
+ firmware: partition@300000 {
+ label = "firmware";
+ compatible = "openwrt,uimage", "denx,uimage";
+ reg = <0x0300000 0x0e80000>;
+ };
+
+ partition@1180000 {
+ label = "runtime2";
+ reg = <0x1180000 0x0e80000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit.dtsi"
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "netgear,gs108t-v3", "realtek,rtl838x-soc";
+ model = "Netgear GS108T v3";
+
+ aliases {
+ led-boot = &led_power_green;
+ led-failsafe = &led_power_amber;
+ led-running = &led_power_green;
+ led-upgrade = &led_power_amber;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power_amber: led-0 {
+ label = "amber:power";
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ };
+
+ led_power_green: led-1 {
+ label = "green:power";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&firmware {
+ openwrt,ih-magic = <0x4e474520>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "netgear,gs110tpp-v1", "realtek,rtl838x-soc";
+ model = "Netgear GS110TPP v1";
+
+ aliases {
+ led-boot = &led_status_green;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_blue;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_red: led-0 {
+ label = "red:status";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_green: led-1 {
+ label = "green:status";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_blue: led-2 {
+ label = "blue:status";
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&firmware {
+ openwrt,ih-magic = <0x4e474520>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&mdio {
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(16, 9, qsgmii)
+ SWITCH_PORT(17, 10, qsgmii)
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "netgear,gs110tup-v1", "realtek,rtl838x-soc";
+ model = "Netgear GS110TUP v1";
+
+ aliases {
+ led-boot = &led_status_green;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_blue;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_red: led-0 {
+ label = "red:status";
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_green: led-1 {
+ label = "green:status";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_blue: led-2 {
+ label = "blue:status";
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&firmware {
+ openwrt,ih-magic = <0x4e474720>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&mdio {
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(24)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(16, 9, qsgmii)
+ SWITCH_SFP_PORT(24, 10, rgmii-id)
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit.dtsi"
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "netgear,gs308t-v1", "realtek,rtl838x-soc";
+ model = "Netgear GS308T v1";
+
+ aliases {
+ led-boot = &led_power_green;
+ led-failsafe = &led_power_amber;
+ led-running = &led_power_green;
+ led-upgrade = &led_power_amber;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power_amber: led-0 {
+ label = "amber:power";
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ };
+
+ led_power_green: led-1 {
+ label = "green:power";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&firmware {
+ openwrt,ih-magic = <0x4e474335>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_netgear_gigabit.dtsi"
+
+/ {
+ compatible = "netgear,gs310tp-v1", "realtek,rtl838x-soc";
+ model = "Netgear GS310TP v1";
+
+};
+
+&firmware {
+ openwrt,ih-magic = <0x4e474335>;
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&mdio {
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+};
+
+&switch0 {
+ ports {
+ SWITCH_SFP_PORT(24, 9, rgmii-id)
+ SWITCH_SFP_PORT(26, 10, rgmii-id)
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "panasonic,m8eg-pn28080k", "realtek,rtl8380-soc";
+ model = "Panasonic Switch-M8eG PN28080K";
+
+ aliases {
+ led-boot = &led_status_eco_green;
+ led-failsafe = &led_status_eco_amber;
+ led-running = &led_status_eco_green;
+ led-upgrade = &led_status_eco_green;
+ };
+
+ sfp0: sfp-p9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&leds {
+ led_status_eco_amber: led-5 {
+ label = "amber:status_eco";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ };
+
+ led_status_eco_green: led-6 {
+ label = "green:status_eco";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ };
+};
+
+&i2c_gpio_0 {
+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c_gpio_1 {
+ scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&gpio1 {
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&gpio2 {
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+};
+
+&i2c_switch {
+ i2c0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ INTERNAL_PHY(24)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@24 {
+ reg = <24>;
+ label = "lan9";
+ phy-mode = "1000base-x";
+ phy-handle = <&phy24>;
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_tplink_sg2xxx.dtsi"
+
+/ {
+ compatible = "tplink,sg2008p-v1", "realtek,rtl838x-soc";
+ model = "TP-Link SG2008P v1";
+};
+
+&tps23861_20 {
+ status = "disabled";
+};
+
+&phy24 {
+ status = "disabled";
+};
+
+&phy26 {
+ status = "disabled";
+};
+
+&port24 {
+ status = "disabled";
+};
+
+&port26 {
+ status = "disabled";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_tplink_sg2xxx.dtsi"
+
+/ {
+ compatible = "tplink,sg2210p-v3", "realtek,rtl838x-soc";
+ model = "TP-Link SG2210P v3";
+};
+
+&port24 {
+ label = "lan-sfp2";
+};
+
+&port26 {
+ label = "lan-sfp1";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ label-mac-device = ðernet0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: led-0 {
+ label = "green:power";
+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tps23861_20: tps23861@20 {
+ compatible = "ti,tps23861";
+ reg = <0x20>;
+ shunt-resistor-micro-ohms = <255000>;
+ };
+
+ tps23861_28: tps23861@28 {
+ compatible = "ti,tps23861";
+ reg = <0x28>;
+ shunt-resistor-micro-ohms = <255000>;
+ };
+ };
+
+ watchdog {
+ compatible = "linux,wdt-gpio";
+ gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+ hw_algo = "toggle";
+ /* SGM706 specs: typical 1.6s, but minimum 1.0s. */
+ hw_margin_ms = <1000>;
+ };
+};
+
+&gpio0 {
+ watchdog-enable {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "watchdog-enable";
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0xe0000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0xe0000 0x20000>;
+ };
+ partition@100000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x100000 0x1a00000>;
+ };
+ partition@1b00000 {
+ label = "usrappfs";
+ reg = <0x1b00000 0x400000>;
+ };
+ partition@1f00000 {
+ label = "para";
+ reg = <0x1f00000 0x100000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ factory_macaddr: macaddr@fdff4 {
+ reg = <0xfdff4 0x6>;
+ };
+ };
+ };
+ };
+ };
+};
+
+ðernet0 {
+ nvmem-cells = <&factory_macaddr>;
+ nvmem-cell-names = "mac-address";
+
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(15, 1, internal)
+ SWITCH_PORT(14, 2, internal)
+ SWITCH_PORT(13, 3, internal)
+ SWITCH_PORT(12, 4, internal)
+ SWITCH_PORT(11, 5, internal)
+ SWITCH_PORT(10, 6, internal)
+ SWITCH_PORT(9, 7, internal)
+ SWITCH_PORT(8, 8, internal)
+
+ SWITCH_SFP_PORT(24, 9, 1000base-x)
+ SWITCH_SFP_PORT(26, 10, 1000base-x)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-10hp", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-10HP Switch";
+
+ /* i2c of the left SFP cage: port 9 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c of the right SFP cage: port 10 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p10 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&mdio {
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+};
+
+&switch0 {
+ ports {
+ port@24 {
+ reg = <24>;
+ label = "lan9";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan10";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-8", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-8 Switch";
+};
+
+&gpio1 {
+ /delete-node/ poe_enable;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-8hp-v1", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-8HP v1 Switch";
+};
+
+&uart1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-8hp-v2", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-8HP v2 Switch";
+};
+
+&uart1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ led-boot = &led_sys;
+ led-failsafe = &led_sys;
+ led-running = &led_sys;
+ led-upgrade = &led_sys;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+ compatible = "gpio-leds";
+
+ led_sys: sys {
+ label = "green:sys";
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+
+ poe_enable {
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+ partition@50000 {
+ label = "u-boot-env2";
+ reg = <0x50000 0x10000>;
+ };
+ partition@60000 {
+ label = "jffs";
+ reg = <0x60000 0x100000>;
+ };
+ partition@160000 {
+ label = "jffs2";
+ reg = <0x160000 0x100000>;
+ };
+ partition@b260000 {
+ label = "firmware";
+ reg = <0x260000 0x6d0000>;
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x83800000>;
+ };
+ partition@930000 {
+ label = "runtime2";
+ reg = <0x930000 0x6d0000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
+ model = "ALLNET ALL-SG8208M";
+
+ aliases {
+ led-boot = &led_sys;
+ led-failsafe = &led_sys;
+ led-running = &led_sys;
+ led-upgrade = &led_sys;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ /* is this pin 3 on the external RTL8231 (&gpio1)? */
+ /*reset {
+ label = "reset";
+ gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };*/
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+ compatible = "gpio-leds";
+
+ led_sys: sys {
+ label = "green:sys";
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+ // GPIO 25: power on/off all port leds
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ read-only;
+ };
+
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@a0000 {
+ label = "jffs";
+ reg = <0xa0000 0x100000>;
+ };
+
+ partition@1a0000 {
+ label = "jffs2";
+ reg = <0x1a0000 0x100000>;
+ };
+
+ partition@2a0000 {
+ label = "firmware";
+ reg = <0x2a0000 0xd60000>;
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x00000006>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "apresia,aplgs120gtss", "realtek,rtl8382-soc";
+ model = "APRESIA ApresiaLightGS120GT-SS";
+
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_power: led-0 {
+ label = "green:pwr";
+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ led-1 {
+ label = "red:loop";
+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_FAULT;
+ };
+
+ /* LED chip is soldered, but no hole on the case */
+ led-2 {
+ label = "green:unused";
+ gpios = <&gpio1 36 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
+ open-source;
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+ };
+
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c-gpio-2 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c-gpio-3 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* 4x TX-Disable lines are provided by RTL8214FC */
+ sfp0: sfp-p17 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ };
+
+ sfp1: sfp-p18 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ };
+
+ sfp2: sfp-p19 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c3>;
+ los-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>;
+ };
+
+ sfp3: sfp-p20 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c2>;
+ los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&gpio0 {
+ rtl8231_reset {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "rtl8231-reset";
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x40000>;
+ };
+
+ partition@c0000 {
+ label = "u-boot-env2";
+ reg = <0xc0000 0x40000>;
+ };
+
+ partition@100000 {
+ compatible = "openwrt,uimage", "denx,uimage";
+ label = "firmware";
+ reg = <0x100000 0xe80000>;
+ openwrt,ih-magic = <0x12345000>;
+ };
+
+ partition@f80000 {
+ label = "firmware2";
+ reg = <0xf80000 0xe80000>;
+ };
+
+ partition@1e00000 {
+ label = "jffs2";
+ reg = <0x1e00000 0x200000>;
+ read-only;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_SFP_PHY_FULL(24, 0)
+ EXTERNAL_SFP_PHY_FULL(25, 1)
+ EXTERNAL_SFP_PHY_FULL(26, 2)
+ EXTERNAL_SFP_PHY_FULL(27, 3)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(24, 17, qsgmii)
+ SWITCH_PORT(25, 18, qsgmii)
+ SWITCH_PORT(26, 19, qsgmii)
+ SWITCH_PORT(27, 20, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_d-link_dgs-1210_common.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-10p", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-10P";
+
+ /* i2c of the left SFP cage: port 9 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c of the right SFP cage: port 10 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p10 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ mode {
+ label = "mode";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_LIGHTS_TOGGLE>;
+ };
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ leds {
+ link_act {
+ label = "green:link_act";
+ gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ };
+
+ poe {
+ label = "green:poe";
+ gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ };
+
+ poe_max {
+ label = "yellow:poe_max";
+ gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ port@24 {
+ reg = <24>;
+ label = "lan9";
+ phy-handle = <&phy24>;
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan10";
+ phy-handle = <&phy26>;
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_d-link_dgs-1210_common.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-16", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-16";
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_SFP_PHY(24)
+ EXTERNAL_SFP_PHY(25)
+ EXTERNAL_SFP_PHY(26)
+ EXTERNAL_SFP_PHY(27)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(24, 17, qsgmii)
+ SWITCH_PORT(25, 18, qsgmii)
+ SWITCH_PORT(26, 19, qsgmii)
+ SWITCH_PORT(27, 20, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_d-link_dgs-1210_common.dtsi"
+#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-20", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-20";
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_SFP_PHY(24)
+ EXTERNAL_SFP_PHY(25)
+ EXTERNAL_SFP_PHY(26)
+ EXTERNAL_SFP_PHY(27)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(24, 17, qsgmii)
+ SWITCH_PORT(25, 18, qsgmii)
+ SWITCH_PORT(26, 19, qsgmii)
+ SWITCH_PORT(27, 20, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_d-link_dgs-1210_common.dtsi"
+#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
+#include "rtl8382_d-link_dgs-1210-28_common.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-28", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-28";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ EXTERNAL_SFP_PHY(24)
+ EXTERNAL_SFP_PHY(25)
+ EXTERNAL_SFP_PHY(26)
+ EXTERNAL_SFP_PHY(27)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ SWITCH_PORT(24, 25, qsgmii)
+ SWITCH_PORT(25, 26, qsgmii)
+ SWITCH_PORT(26, 27, qsgmii)
+ SWITCH_PORT(27, 28, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_d-link_dgs-1210_common.dtsi"
+#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
+#include "rtl8382_d-link_dgs-1210-28_common.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-28mp-f", "realtek,rtl8382-soc", "realtek,rtl838x-soc";
+ model = "D-Link DGS-1210-28MP F";
+};
+
+&leds {
+ link_act {
+ label = "green:link_act";
+ gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ };
+
+ poe {
+ label = "green:poe";
+ gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ };
+
+ poe_max {
+ label = "yellow:poe_max";
+ gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&keys {
+ mode {
+ label = "mode";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8382_hpe_1920.dtsi"
+
+/ {
+ compatible = "hpe,1920-16g", "realtek,rtl838x-soc";
+ model = "HPE 1920-16G (JG923A)";
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ SWITCH_PORT(16, 9, qsgmii)
+ SWITCH_PORT(17, 10, qsgmii)
+ SWITCH_PORT(18, 11, qsgmii)
+ SWITCH_PORT(19, 12, qsgmii)
+ SWITCH_PORT(20, 13, qsgmii)
+ SWITCH_PORT(21, 14, qsgmii)
+ SWITCH_PORT(22, 15, qsgmii)
+ SWITCH_PORT(23, 16, qsgmii)
+
+ SWITCH_PORT(24, 17, qsgmii)
+ SWITCH_PORT(25, 18, qsgmii)
+ SWITCH_PORT(26, 19, qsgmii)
+ SWITCH_PORT(27, 20, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl8382_hpe_1920.dtsi"
+
+/ {
+ compatible = "hpe,1920-24g", "realtek,rtl838x-soc";
+ model = "HPE 1920-24G (JG924A)";
+};
+
+&mdio {
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ SWITCH_PORT(24, 25, qsgmii)
+ SWITCH_PORT(25, 26, qsgmii)
+ SWITCH_PORT(26, 27, qsgmii)
+ SWITCH_PORT(27, 28, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl838x_hpe_1920.dtsi"
+
+/ {
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+ };
+
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ // tx-fault unconnected
+ // tx-disable connected to RTL8214FC
+ };
+
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ // tx-fault unconnected
+ // tx-disable connected to RTL8214FC
+ };
+
+ i2c2: i2c-gpio-2 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp2: sfp-2 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c2>;
+ los-gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ // tx-fault unconnected
+ // tx-disable connected to RTL8214FC
+ };
+
+ i2c3: i2c-gpio-3 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 32 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp3: sfp-3 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c3>;
+ los-gpio = <&gpio1 34 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 33 GPIO_ACTIVE_LOW>;
+ // tx-fault unconnected
+ // tx-disable connected to RTL8214FC
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ EXTERNAL_SFP_PHY_FULL(24, 0)
+ EXTERNAL_SFP_PHY_FULL(25, 1)
+ EXTERNAL_SFP_PHY_FULL(26, 2)
+ EXTERNAL_SFP_PHY_FULL(27, 3)
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "inaba,aml2-17gp", "realtek,rtl838x-soc";
+ model = "INABA Abaniact AML2-17GP";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ read-only;
+ };
+
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@a0000 {
+ label = "jffs2_cfg";
+ reg = <0xa0000 0x400000>;
+ read-only;
+ };
+
+ partition@4a0000 {
+ label = "jffs2_log";
+ reg = <0x4a0000 0x100000>;
+ read-only;
+ };
+
+ partition@5a0000 {
+ compatible = "openwrt,uimage", "denx,uimage";
+ label = "firmware";
+ reg = <0x5a0000 0xd30000>;
+ openwrt,ih-magic = <0x83800000>;
+ };
+
+ partition@12d0000 {
+ label = "runtime2";
+ reg = <0x12d0000 0xd30000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ EXTERNAL_PHY(24)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ SWITCH_PORT(16, 9, qsgmii)
+ SWITCH_PORT(17, 10, qsgmii)
+ SWITCH_PORT(18, 11, qsgmii)
+ SWITCH_PORT(19, 12, qsgmii)
+ SWITCH_PORT(20, 13, qsgmii)
+ SWITCH_PORT(21, 14, qsgmii)
+ SWITCH_PORT(22, 15, qsgmii)
+ SWITCH_PORT(23, 16, qsgmii)
+
+ port@24 {
+ reg = <24>;
+ label = "wan";
+ phy-handle = <&phy24>;
+ phy-mode = "qsgmii";
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "iodata,bsh-g24mb", "realtek,rtl838x-soc";
+ model = "I-O DATA BSH-G24MB";
+
+ aliases {
+ led-boot = &led_sys_loop;
+ led-failsafe = &led_sys_loop;
+ led-upgrade = &led_sys_loop;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+ compatible = "gpio-leds";
+
+ led_sys_loop: led {
+ label = "red:sys_loop";
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ read-only;
+ };
+
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@a0000 {
+ label = "jffs2_cfg";
+ reg = <0xa0000 0x100000>;
+ read-only;
+ };
+
+ partition@1a0000 {
+ label = "jffs2_log";
+ reg = <0x1a0000 0x100000>;
+ read-only;
+ };
+
+ /*
+ * use 2x OS partitions in OpenWrt
+ *
+ * 0x2A0000-0x94FFFF: RUNTIME
+ * 0x950000-0xFFFFFF: RUNTIME2 (not used in stock)
+ */
+ partition@2a0000 {
+ compatible = "openwrt,uimage", "denx,uimage";
+ label = "firmware";
+ reg = <0x2a0000 0xd60000>;
+ openwrt,ih-magic = <0x83800013>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "panasonic,m16eg-pn28160k", "realtek,rtl8382-soc";
+ model = "Panasonic Switch-M16eG PN28160K";
+
+ aliases {
+ led-boot = &led_status_eco_green;
+ led-failsafe = &led_status_eco_amber;
+ led-running = &led_status_eco_green;
+ led-upgrade = &led_status_eco_green;
+ };
+
+ /*
+ * sfp0/1 are "combo" port with each TP port (23/24), and they are
+ * connected to the RTL8218FB. Currently, there is no support for
+ * the chip and only TP ports work by the RTL8218D support.
+ */
+ sfp0: sfp-p23 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp-p24 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&leds {
+ led_status_eco_amber: led-5 {
+ label = "amber:status_eco";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ };
+
+ led_status_eco_green: led-6 {
+ label = "green:status_eco";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ };
+};
+
+&i2c_gpio_0 {
+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c_gpio_1 {
+ scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&gpio2 {
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+
+ /*
+ * GPIO12 (IO1_4): RTL8218FB
+ *
+ * This GPIO pin should be specified as "reset-gpio" in mdio node, but
+ * RTL8218FB phy won't be configured on RTL8218D support in the current
+ * phy driver. So, ethernet ports on the phy will be broken after hard-
+ * resetting.
+ * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
+ * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
+ * by resetting.
+ */
+ ext_switch_reset {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "ext-switch-reset";
+ };
+};
+
+&i2c_switch {
+ i2c0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ /* RTL8218FB */
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(8, 1, internal)
+ SWITCH_PORT(9, 2, internal)
+ SWITCH_PORT(10, 3, internal)
+ SWITCH_PORT(11, 4, internal)
+ SWITCH_PORT(12, 5, internal)
+ SWITCH_PORT(13, 6, internal)
+ SWITCH_PORT(14, 7, internal)
+ SWITCH_PORT(15, 8, internal)
+
+ SWITCH_PORT(16, 9, qsgmii)
+ SWITCH_PORT(17, 10, qsgmii)
+ SWITCH_PORT(18, 11, qsgmii)
+ SWITCH_PORT(19, 12, qsgmii)
+ SWITCH_PORT(20, 13, qsgmii)
+ SWITCH_PORT(21, 14, qsgmii)
+ SWITCH_PORT(22, 15, qsgmii)
+ SWITCH_PORT(23, 16, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "panasonic,m24eg-pn28240k", "realtek,rtl8382-soc";
+ model = "Panasonic Switch-M24eG PN28240K";
+
+ aliases {
+ led-boot = &led_status_eco_green;
+ led-failsafe = &led_status_eco_amber;
+ led-running = &led_status_eco_green;
+ led-upgrade = &led_status_eco_green;
+ };
+
+ /*
+ * sfp0/1 are "combo" port with each TP port (23/24), and they are
+ * connected to the RTL8218FB. Currently, there is no support for
+ * the chip and only TP ports work by the RTL8218D support.
+ */
+ sfp0: sfp-p23 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp-p24 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&leds {
+ led_status_eco_amber: led-5 {
+ label = "amber:status_eco";
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ };
+
+ led_status_eco_green: led-6 {
+ label = "green:status_eco";
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ };
+};
+
+&i2c_gpio_0 {
+ scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&i2c_gpio_1 {
+ scl-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&gpio2 {
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+
+ /*
+ * GPIO12 (IO1_4): RTL8218B + RTL8218FB
+ *
+ * This GPIO pin should be specified as "reset-gpio" in mdio node,
+ * but the current configuration of RTL8218B phy in the phy driver
+ * seems to be incomplete and RTL8218FB phy won't be configured on
+ * RTL8218D support. So, ethernet ports on these phys will be broken
+ * after hard-resetting.
+ * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
+ * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
+ * by resetting.
+ */
+ ext_switch_reset {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "ext-switch-reset";
+ };
+};
+
+&i2c_switch {
+ i2c0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ /* RTL8218FB */
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl838x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "tplink,t1600g-28ts-v3", "realtek,rtl838x-soc";
+ model = "TP-Link T1600G-28TS v3";
+
+ aliases {
+ led-boot = &led_sys;
+ led-failsafe = &led_sys;
+ led-running = &led_sys;
+ led-upgrade = &led_sys;
+ label-mac-device = ðernet0;
+ };
+
+ chosen {
+ stdout-path = "serial0:38400n8";
+ };
+
+ leds {
+ pinctrl-names = "default";
+ compatible = "gpio-leds";
+
+ led_sys: led-0 {
+ label = "green:sys";
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0xe0000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0xe0000 0x20000>;
+ };
+ partition@100000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x100000 0x1a00000>;
+ };
+ partition@1b00000 {
+ label = "usrappfs";
+ reg = <0x1b00000 0x400000>;
+ };
+ partition@1f00000 {
+ label = "para";
+ reg = <0x1f00000 0x100000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ factory_macaddr: macaddr@fdff4 {
+ reg = <0xfdff4 0x6>;
+ };
+ };
+ };
+ };
+ };
+};
+
+ðernet0 {
+ nvmem-cells = <&factory_macaddr>;
+ nvmem-cell-names = "mac-address";
+
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ INTERNAL_PHY(8)
+ INTERNAL_PHY(9)
+ INTERNAL_PHY(10)
+ INTERNAL_PHY(11)
+ INTERNAL_PHY(12)
+ INTERNAL_PHY(13)
+ INTERNAL_PHY(14)
+ INTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-16", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-16";
+};
+
+&mdio {
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(16, 9, qsgmii)
+ SWITCH_PORT(17, 10, qsgmii)
+ SWITCH_PORT(18, 11, qsgmii)
+ SWITCH_PORT(19, 12, qsgmii)
+ SWITCH_PORT(20, 13, qsgmii)
+ SWITCH_PORT(21, 14, qsgmii)
+ SWITCH_PORT(22, 15, qsgmii)
+ SWITCH_PORT(23, 16, qsgmii)
+ };
+};
+
+&gpio1 {
+ /delete-node/ poe_enable;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-24-v1", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-24 v1";
+
+ memory@0 {
+ reg = <0x0 0x4000000>;
+ };
+
+ /* i2c of the left SFP cage: port 25 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p25 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c of the right SFP cage: port 26 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p26 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&mdio {
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ port@24 {
+ reg = <24>;
+ label = "lan25";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan26";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+ };
+};
+
+&gpio1 {
+ /delete-node/ poe_enable;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-24e", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-24E";
+};
+
+&mdio {
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(1, 1, qsgmii)
+ SWITCH_PORT(0, 2, qsgmii)
+ SWITCH_PORT(3, 3, qsgmii)
+ SWITCH_PORT(2, 4, qsgmii)
+ SWITCH_PORT(5, 5, qsgmii)
+ SWITCH_PORT(4, 6, qsgmii)
+ SWITCH_PORT(7, 7, qsgmii)
+ SWITCH_PORT(6, 8, qsgmii)
+
+ SWITCH_PORT(9, 9, internal)
+ SWITCH_PORT(8, 10, internal)
+ SWITCH_PORT(11, 11, internal)
+ SWITCH_PORT(10, 12, internal)
+ SWITCH_PORT(13, 13, internal)
+ SWITCH_PORT(12, 14, internal)
+ SWITCH_PORT(15, 15, internal)
+ SWITCH_PORT(14, 16, internal)
+
+ SWITCH_PORT(17, 17, qsgmii)
+ SWITCH_PORT(16, 18, qsgmii)
+ SWITCH_PORT(19, 19, qsgmii)
+ SWITCH_PORT(18, 20, qsgmii)
+ SWITCH_PORT(21, 21, qsgmii)
+ SWITCH_PORT(20, 22, qsgmii)
+ SWITCH_PORT(23, 23, qsgmii)
+ SWITCH_PORT(22, 24, qsgmii)
+ };
+};
+
+&gpio1 {
+ /delete-node/ poe_enable;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-24hp-v1", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-24HP v1";
+
+ memory@0 {
+ reg = <0x0 0x4000000>;
+ };
+
+ /* i2c of the left SFP cage: port 25 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p25 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c of the right SFP cage: port 26 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p26 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&mdio {
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ port@24 {
+ reg = <24>;
+ label = "lan25";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan26";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+ };
+};
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#include "rtl8380_zyxel_gs1900.dtsi"
+
+/ {
+ compatible = "zyxel,gs1900-24hp-v2", "realtek,rtl838x-soc";
+ model = "ZyXEL GS1900-24HP v2 Switch";
+
+ /* i2c of the left SFP cage: port 25 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p25 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c of the right SFP cage: port 26 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p26 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&mdio {
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ INTERNAL_PHY(24)
+ INTERNAL_PHY(26)
+};
+
+&switch0 {
+ ports {
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, internal)
+ SWITCH_PORT(9, 10, internal)
+ SWITCH_PORT(10, 11, internal)
+ SWITCH_PORT(11, 12, internal)
+ SWITCH_PORT(12, 13, internal)
+ SWITCH_PORT(13, 14, internal)
+ SWITCH_PORT(14, 15, internal)
+ SWITCH_PORT(15, 16, internal)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+
+ port@24 {
+ reg = <24>;
+ label = "lan25";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp0>;
+ };
+
+ port@26 {
+ reg = <26>;
+ label = "lan26";
+ phy-mode = "1000base-x";
+ managed = "in-band-status";
+ sfp = <&sfp1>;
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/clock/rtl83xx-clk.h>
+
+/dts-v1/;
+
+#define STRINGIZE(s) #s
+#define LAN_LABEL(p, s) STRINGIZE(p ## s)
+#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
+
+#define INTERNAL_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ reg = <##n>; \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ phy-is-integrated; \
+ };
+
+#define EXTERNAL_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ reg = <##n>; \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ };
+
+#define EXTERNAL_SFP_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ sfp; \
+ media = "fibre"; \
+ reg = <##n>; \
+ };
+
+#define EXTERNAL_SFP_PHY_FULL(n, s) \
+ phy##n: ethernet-phy@##n { \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ sfp = <&sfp##s>; \
+ reg = <##n>; \
+ };
+
+#define SWITCH_PORT(n, s, m) \
+ port##n: port@##n { \
+ reg = <##n>; \
+ label = SWITCH_PORT_LABEL(s) ; \
+ phy-handle = <&phy##n>; \
+ phy-mode = #m ; \
+ };
+
+#define SWITCH_SFP_PORT(n, s, m) \
+ port##n: port@##n { \
+ reg = <##n>; \
+ label = SWITCH_PORT_LABEL(s) ; \
+ phy-handle = <&phy##n>; \
+ phy-mode = #m ; \
+ fixed-link { \
+ speed = <1000>; \
+ full-duplex; \
+ }; \
+ };
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "realtek,rtl838x-soc";
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ ccu: clock-controller {
+ compatible = "realtek,rtl8380-clock";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ clock-names = "ref_clk";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips4KEc";
+ reg = <0>;
+ clocks = <&ccu CLK_CPU>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+
+ cpu_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <325000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <350000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <375000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <400000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <425000000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <450000000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <475000000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <500000000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpuintc: cpuintc {
+ compatible = "mti,cpu-interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000000 0x10000>;
+
+ intc: interrupt-controller@3000 {
+ compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
+ reg = <0x3000 0x18>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>, <4>, <5>, <6>;
+ };
+
+ spi0: spi@1200 {
+ compatible = "realtek,rtl8380-spi";
+ reg = <0x1200 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer0: timer@3100 {
+ compatible = "realtek,rtl8380-timer", "realtek,otto-timer";
+ reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
+ <0x3130 0x10>, <0x3140 0x10>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
+ clocks = <&ccu CLK_LXB>;
+ };
+
+ uart0: uart@2000 {
+ compatible = "ns16550a";
+ reg = <0x2000 0x100>;
+
+ clocks = <&ccu CLK_LXB>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <31 1>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+ };
+
+ uart1: uart@2100 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&enable_uart1>;
+
+ compatible = "ns16550a";
+ reg = <0x2100 0x100>;
+
+ clocks = <&ccu CLK_LXB>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30 0>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@3150 {
+ compatible = "realtek,rtl8380-wdt";
+ reg = <0x3150 0xc>;
+
+ realtek,reset-mode = "soc";
+
+ clocks = <&ccu CLK_LXB>;
+ timeout-sec = <30>;
+
+ interrupt-parent = <&intc>;
+ interrupt-names = "phase1", "phase2";
+ interrupts = <19 3>, <18 4>;
+ };
+
+ gpio0: gpio-controller@3500 {
+ compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
+ reg = <0x3500 0x20>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <24>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <23 3>;
+ };
+ };
+
+ pinmux: pinmux@1b001000 {
+ compatible = "pinctrl-single";
+ reg = <0x1b001000 0x4>;
+
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x1>;
+ #pinctrl-cells = <2>;
+
+ enable_uart1: pinmux_enable_uart1 {
+ pinctrl-single,bits = <0x0 0x10 0x10>;
+ };
+ };
+
+ /* LED_GLB_CTRL */
+ pinmux_led: pinmux@1b00a000 {
+ compatible = "pinctrl-single";
+ reg = <0x1b00a000 0x4>;
+
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x1>;
+ #pinctrl-cells = <2>;
+
+ /* enable GPIO 0 */
+ pinmux_disable_sys_led: disable_sys_led {
+ pinctrl-single,bits = <0x0 0x0 0x8000>;
+ };
+ };
+
+ ethernet0: ethernet@1b00a300 {
+ compatible = "realtek,rtl838x-eth";
+ reg = <0x1b00a300 0x100>;
+ interrupt-parent = <&intc>;
+ interrupts = <24 3>;
+ #interrupt-cells = <1>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ sram0: sram@9f000000 {
+ compatible = "mmio-sram";
+ reg = <0x9f000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x9f000000 0x10000>;
+ };
+
+ switch0: switch@1b000000 {
+ compatible = "realtek,rtl83xx-switch";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20 2>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ chosen {
+ stdout-path = "serial0:38400n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ watchdog1: watchdog {
+ // PT7A7514
+ compatible = "linux,wdt-gpio";
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ hw_algo = "toggle";
+ hw_margin_ms = <1000>;
+ always-running;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+ };
+};
+
+&watchdog0 {
+ status = "disabled";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bootware_basic";
+ reg = <0x0 0x50000>;
+ read-only;
+ };
+
+ partition@60000 {
+ label = "bootware_data";
+ reg = <0x60000 0x30000>;
+ read-only;
+ };
+
+ partition@90000 {
+ label = "bootware_extend";
+ reg = <0x90000 0x40000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "bootware_basic_backup";
+ reg = <0x100000 0x50000>;
+ read-only;
+ };
+
+ partition@160000 {
+ label = "bootware_data_backup";
+ reg = <0x160000 0x30000>;
+ read-only;
+ };
+
+ partition@190000 {
+ label = "bootware_extend_backup";
+ reg = <0x190000 0x40000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "firmware";
+ compatible = "h3c,vfs-firmware";
+ reg = <0x300000 0x1cf0000>;
+ };
+
+ partition@1ff0000 {
+ label = "factory";
+ reg = <0x1ff0000 0x10000>;
+ read-only;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl839x.dtsi"
+#include "rtl83xx_d-link_dgs-1210_common.dtsi"
+#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
+#include "rtl839x_d-link_dgs-1210_gpio.dtsi"
+
+/ {
+ compatible = "d-link,dgs-1210-52", "realtek,rtl8393-soc";
+ model = "D-Link DGS-1210-52";
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* External phy RTL8218B #1 */
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ /* External phy RTL8218B #2 */
+ EXTERNAL_PHY(8)
+ EXTERNAL_PHY(9)
+ EXTERNAL_PHY(10)
+ EXTERNAL_PHY(11)
+ EXTERNAL_PHY(12)
+ EXTERNAL_PHY(13)
+ EXTERNAL_PHY(14)
+ EXTERNAL_PHY(15)
+
+ /* External phy RTL8218B #3 */
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ /* External phy RTL8218B #4 */
+ EXTERNAL_PHY(24)
+ EXTERNAL_PHY(25)
+ EXTERNAL_PHY(26)
+ EXTERNAL_PHY(27)
+ EXTERNAL_PHY(28)
+ EXTERNAL_PHY(29)
+ EXTERNAL_PHY(30)
+ EXTERNAL_PHY(31)
+
+ /* External phy RTL8218B #5 */
+ EXTERNAL_PHY(32)
+ EXTERNAL_PHY(33)
+ EXTERNAL_PHY(34)
+ EXTERNAL_PHY(35)
+ EXTERNAL_PHY(36)
+ EXTERNAL_PHY(37)
+ EXTERNAL_PHY(38)
+ EXTERNAL_PHY(39)
+
+ /* External phy RTL8218B #6 */
+ EXTERNAL_PHY(40)
+ EXTERNAL_PHY(41)
+ EXTERNAL_PHY(42)
+ EXTERNAL_PHY(43)
+ EXTERNAL_PHY(44)
+ EXTERNAL_PHY(45)
+ EXTERNAL_PHY(46)
+ EXTERNAL_PHY(47)
+
+ /* External phy RTL8214FC */
+ EXTERNAL_SFP_PHY_FULL(48, 0)
+ EXTERNAL_SFP_PHY_FULL(49, 1)
+ EXTERNAL_SFP_PHY_FULL(50, 2)
+ EXTERNAL_SFP_PHY_FULL(51, 3)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, qsgmii)
+ SWITCH_PORT(9, 10, qsgmii)
+ SWITCH_PORT(10, 11, qsgmii)
+ SWITCH_PORT(11, 12, qsgmii)
+ SWITCH_PORT(12, 13, qsgmii)
+ SWITCH_PORT(13, 14, qsgmii)
+ SWITCH_PORT(14, 15, qsgmii)
+ SWITCH_PORT(15, 16, qsgmii)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ SWITCH_PORT(24, 25, qsgmii)
+ SWITCH_PORT(25, 26, qsgmii)
+ SWITCH_PORT(26, 27, qsgmii)
+ SWITCH_PORT(27, 28, qsgmii)
+ SWITCH_PORT(28, 29, qsgmii)
+ SWITCH_PORT(29, 30, qsgmii)
+ SWITCH_PORT(30, 31, qsgmii)
+ SWITCH_PORT(31, 32, qsgmii)
+
+ SWITCH_PORT(32, 33, qsgmii)
+ SWITCH_PORT(33, 34, qsgmii)
+ SWITCH_PORT(34, 35, qsgmii)
+ SWITCH_PORT(35, 36, qsgmii)
+ SWITCH_PORT(36, 37, qsgmii)
+ SWITCH_PORT(37, 38, qsgmii)
+ SWITCH_PORT(38, 39, qsgmii)
+ SWITCH_PORT(39, 40, qsgmii)
+
+ SWITCH_PORT(40, 41, qsgmii)
+ SWITCH_PORT(41, 42, qsgmii)
+ SWITCH_PORT(42, 43, qsgmii)
+ SWITCH_PORT(43, 44, qsgmii)
+ SWITCH_PORT(44, 45, qsgmii)
+ SWITCH_PORT(45, 46, qsgmii)
+ SWITCH_PORT(46, 47, qsgmii)
+ SWITCH_PORT(47, 48, qsgmii)
+
+ SWITCH_PORT(48, 49, qsgmii)
+ SWITCH_PORT(49, 50, qsgmii)
+ SWITCH_PORT(50, 51, qsgmii)
+ SWITCH_PORT(51, 52, qsgmii)
+
+ /* CPU-Port */
+ port@52 {
+ ethernet = <ðernet0>;
+ reg = <52>;
+ phy-mode = "qsgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl839x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "netgear,gs750e", "realtek,rtl8393-soc";
+ model = "Netgear GS750E";
+
+ aliases {
+ label-mac-device = ðernet0;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
+ };
+
+ virtual_flash {
+ compatible = "mtd-concat";
+
+ devices = <&fwconcat0>, <&fwconcat1>, <&fwconcat2>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "firmware";
+ reg = <0x0 0x760000>;
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x174e4741>;
+ };
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ read-only;
+ };
+
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ read-only;
+ };
+
+ fwconcat1: partition@a0000 {
+ label = "jffs2_cfg";
+ reg = <0xa0000 0x80000>;
+ };
+
+ fwconcat2: partition@120000 {
+ label = "jffs2_log";
+ reg = <0x120000 0x80000>;
+ };
+
+ fwconcat0: partition@1a0000 {
+ label = "runtime";
+ reg = <0x1a0000 0x660000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ // Switch doesn't come back properly after a reset so don't.
+ // reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+
+ /* External phy RTL8218B #1 */
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ /* External phy RTL8218B #2 */
+ EXTERNAL_PHY(8)
+ EXTERNAL_PHY(9)
+ EXTERNAL_PHY(10)
+ EXTERNAL_PHY(11)
+ EXTERNAL_PHY(12)
+ EXTERNAL_PHY(13)
+ EXTERNAL_PHY(14)
+ EXTERNAL_PHY(15)
+
+ /* External phy RTL8218B #3 */
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ /* External phy RTL8218B #4 */
+ EXTERNAL_PHY(24)
+ EXTERNAL_PHY(25)
+ EXTERNAL_PHY(26)
+ EXTERNAL_PHY(27)
+ EXTERNAL_PHY(28)
+ EXTERNAL_PHY(29)
+ EXTERNAL_PHY(30)
+ EXTERNAL_PHY(31)
+
+ /* External phy RTL8218B #5 */
+ EXTERNAL_PHY(32)
+ EXTERNAL_PHY(33)
+ EXTERNAL_PHY(34)
+ EXTERNAL_PHY(35)
+ EXTERNAL_PHY(36)
+ EXTERNAL_PHY(37)
+ EXTERNAL_PHY(38)
+ EXTERNAL_PHY(39)
+
+ /* External phy RTL8218B #6 */
+ EXTERNAL_PHY(40)
+ EXTERNAL_PHY(41)
+ EXTERNAL_PHY(42)
+ EXTERNAL_PHY(43)
+ EXTERNAL_PHY(44)
+ EXTERNAL_PHY(45)
+ EXTERNAL_PHY(46)
+ EXTERNAL_PHY(47)
+
+ /* RTL8393 Internal SerDes */
+ INTERNAL_PHY(48)
+ INTERNAL_PHY(49)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, qsgmii)
+ SWITCH_PORT(9, 10, qsgmii)
+ SWITCH_PORT(10, 11, qsgmii)
+ SWITCH_PORT(11, 12, qsgmii)
+ SWITCH_PORT(12, 13, qsgmii)
+ SWITCH_PORT(13, 14, qsgmii)
+ SWITCH_PORT(14, 15, qsgmii)
+ SWITCH_PORT(15, 16, qsgmii)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ SWITCH_PORT(24, 25, qsgmii)
+ SWITCH_PORT(25, 26, qsgmii)
+ SWITCH_PORT(26, 27, qsgmii)
+ SWITCH_PORT(27, 28, qsgmii)
+ SWITCH_PORT(28, 29, qsgmii)
+ SWITCH_PORT(29, 30, qsgmii)
+ SWITCH_PORT(30, 31, qsgmii)
+ SWITCH_PORT(31, 32, qsgmii)
+
+ SWITCH_PORT(32, 33, qsgmii)
+ SWITCH_PORT(33, 34, qsgmii)
+ SWITCH_PORT(34, 35, qsgmii)
+ SWITCH_PORT(35, 36, qsgmii)
+ SWITCH_PORT(36, 37, qsgmii)
+ SWITCH_PORT(37, 38, qsgmii)
+ SWITCH_PORT(38, 39, qsgmii)
+ SWITCH_PORT(39, 40, qsgmii)
+
+ SWITCH_PORT(40, 41, qsgmii)
+ SWITCH_PORT(41, 42, qsgmii)
+ SWITCH_PORT(42, 43, qsgmii)
+ SWITCH_PORT(43, 44, qsgmii)
+ SWITCH_PORT(44, 45, qsgmii)
+ SWITCH_PORT(45, 46, qsgmii)
+ SWITCH_PORT(46, 47, qsgmii)
+ SWITCH_PORT(47, 48, qsgmii)
+
+ /* SFP cages */
+ SWITCH_SFP_PORT(48, 49, sgmii)
+ SWITCH_SFP_PORT(49, 50, sgmii)
+
+ /* CPU-Port */
+ port@52 {
+ ethernet = <ðernet0>;
+ reg = <52>;
+ phy-mode = "qsgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl839x.dtsi"
+#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "panasonic,m48eg-pn28480k", "realtek,rtl8393-soc";
+ model = "Panasonic Switch-M48eG PN28480K";
+
+ aliases {
+ led-boot = &led_status_eco_green;
+ led-failsafe = &led_status_eco_amber;
+ led-running = &led_status_eco_green;
+ led-upgrade = &led_status_eco_green;
+ };
+
+ fan: gpio-fan {
+ compatible = "gpio-fan";
+ gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+ /* the actual speeds (rpm) are unknown, just use dummy values */
+ gpio-fan,speed-map = <1 0>, <2 1>;
+ #cooling-cells = <2>;
+ };
+
+ /*
+ * sfp0/1/2/3 are "combo" port with each TP port (45/46/47/48),
+ * and they are connected to the RTL8218FB. Currently, there is
+ * no support for the chip and only TP ports work by the RTL8218B
+ * support.
+ */
+ sfp0: sfp-p45 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp-p46 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp2: sfp-p47 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c2>;
+ tx-fault-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp3: sfp-p48 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c3>;
+ tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ los-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ thermal-zones {
+ /*
+ * Zone for SoC temperature
+ *
+ * Fan speed:
+ *
+ * - 0-44 celsius: Low
+ * - 45-54 celsius: High
+ */
+ cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <2000>;
+
+ thermal-sensors = <&tsens_soc>;
+
+ trips {
+ cpu_alert: trip-point {
+ temperature = <45000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ cpu_crit {
+ temperature = <55000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&cpu_alert>;
+ cooling-device = <&fan 0 1>;
+ };
+ };
+ };
+
+ /*
+ * Zone for system temperature
+ *
+ * Fan speed:
+ *
+ * - 0-39 celsius: Low
+ * - 40-49 celsius: High
+ *
+ * Note: official recommended ranges of temperature on each
+ * fan speed setting:
+ *
+ * - Low speed : 0-40 celsius
+ * - High speed: 0-50 celsius
+ *
+ * (stock firmware doesn't support auto-selection of
+ * speed and need to be selected manually by user)
+ */
+ sys-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <2000>;
+
+ thermal-sensors = <&tsens_sys>;
+
+ trips {
+ sys_alert: trip-point {
+ temperature = <40000>;
+ hysteresis = <4000>;
+ type = "active";
+ };
+
+ sys_crit {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map {
+ trip = <&sys_alert>;
+ cooling-device = <&fan 0 1>;
+ };
+ };
+ };
+ };
+};
+
+&leds {
+ led_status_eco_amber: led-5 {
+ label = "amber:status_eco";
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ };
+
+ led_status_eco_green: led-6 {
+ label = "green:status_eco";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ };
+};
+
+&i2c_gpio_0 {
+ scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ /* Microchip TCN75A (for SoC) */
+ tsens_soc: sensor@48 {
+ compatible = "microchip,tcn75";
+ reg = <0x48>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ /* Microchip TCN75A (for System) */
+ tsens_sys: sensor@49 {
+ compatible = "microchip,tcn75";
+ reg = <0x49>;
+ #thermal-sensor-cells = <0>;
+ };
+};
+
+&i2c_gpio_1 {
+ scl-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+};
+
+&gpio2 {
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ /*
+ * GPIO12 (IO1_4): 5x RTL8218B + RTL8218FB
+ *
+ * This GPIO pin should be specified as "reset-gpio" in mdio node,
+ * but the current configuration of RTL8218B phy in the phy driver
+ * seems to be incomplete and RTL8218FB phy won't be configured on
+ * RTL8218D support. So, ethernet ports on these phys will be broken
+ * after hard-resetting.
+ * (RTL8218FB phy will be detected as RTL8218D by the phy driver)
+ * At the moment, configure this GPIO pin as gpio-hog to avoid breaking
+ * by resetting.
+ */
+ ext_switch_reset {
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "ext-switch-reset";
+ };
+};
+
+&i2c_switch {
+ i2c0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+
+ i2c2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+
+ i2c3: i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ };
+};
+
+ðernet0 {
+ mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ EXTERNAL_PHY(8)
+ EXTERNAL_PHY(9)
+ EXTERNAL_PHY(10)
+ EXTERNAL_PHY(11)
+ EXTERNAL_PHY(12)
+ EXTERNAL_PHY(13)
+ EXTERNAL_PHY(14)
+ EXTERNAL_PHY(15)
+
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ EXTERNAL_PHY(24)
+ EXTERNAL_PHY(25)
+ EXTERNAL_PHY(26)
+ EXTERNAL_PHY(27)
+ EXTERNAL_PHY(28)
+ EXTERNAL_PHY(29)
+ EXTERNAL_PHY(30)
+ EXTERNAL_PHY(31)
+
+ EXTERNAL_PHY(32)
+ EXTERNAL_PHY(33)
+ EXTERNAL_PHY(34)
+ EXTERNAL_PHY(35)
+ EXTERNAL_PHY(36)
+ EXTERNAL_PHY(37)
+ EXTERNAL_PHY(38)
+ EXTERNAL_PHY(39)
+
+ /* RTL8218FB */
+ EXTERNAL_PHY(40)
+ EXTERNAL_PHY(41)
+ EXTERNAL_PHY(42)
+ EXTERNAL_PHY(43)
+ EXTERNAL_PHY(44)
+ EXTERNAL_PHY(45)
+ EXTERNAL_PHY(46)
+ EXTERNAL_PHY(47)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 1, qsgmii)
+ SWITCH_PORT(1, 2, qsgmii)
+ SWITCH_PORT(2, 3, qsgmii)
+ SWITCH_PORT(3, 4, qsgmii)
+ SWITCH_PORT(4, 5, qsgmii)
+ SWITCH_PORT(5, 6, qsgmii)
+ SWITCH_PORT(6, 7, qsgmii)
+ SWITCH_PORT(7, 8, qsgmii)
+
+ SWITCH_PORT(8, 9, qsgmii)
+ SWITCH_PORT(9, 10, qsgmii)
+ SWITCH_PORT(10, 11, qsgmii)
+ SWITCH_PORT(11, 12, qsgmii)
+ SWITCH_PORT(12, 13, qsgmii)
+ SWITCH_PORT(13, 14, qsgmii)
+ SWITCH_PORT(14, 15, qsgmii)
+ SWITCH_PORT(15, 16, qsgmii)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ SWITCH_PORT(24, 25, qsgmii)
+ SWITCH_PORT(25, 26, qsgmii)
+ SWITCH_PORT(26, 27, qsgmii)
+ SWITCH_PORT(27, 28, qsgmii)
+ SWITCH_PORT(28, 29, qsgmii)
+ SWITCH_PORT(29, 30, qsgmii)
+ SWITCH_PORT(30, 31, qsgmii)
+ SWITCH_PORT(31, 32, qsgmii)
+
+ SWITCH_PORT(32, 33, qsgmii)
+ SWITCH_PORT(33, 34, qsgmii)
+ SWITCH_PORT(34, 35, qsgmii)
+ SWITCH_PORT(35, 36, qsgmii)
+ SWITCH_PORT(36, 37, qsgmii)
+ SWITCH_PORT(37, 38, qsgmii)
+ SWITCH_PORT(38, 39, qsgmii)
+ SWITCH_PORT(39, 40, qsgmii)
+
+ SWITCH_PORT(40, 41, qsgmii)
+ SWITCH_PORT(41, 42, qsgmii)
+ SWITCH_PORT(42, 43, qsgmii)
+ SWITCH_PORT(43, 44, qsgmii)
+ SWITCH_PORT(44, 45, qsgmii)
+ SWITCH_PORT(45, 46, qsgmii)
+ SWITCH_PORT(46, 47, qsgmii)
+ SWITCH_PORT(47, 48, qsgmii)
+
+ port@52 {
+ ethernet = <ðernet0>;
+ reg = <52>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rtl839x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "tplink,sg2452p-v4", "realtek,rtl8393-soc";
+ model = "TP-Link SG2452P v4";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ aliases {
+ led-boot = &led_sys;
+ led-failsafe = &led_sys;
+ led-running = &led_sys;
+ led-upgrade = &led_sys;
+ label-mac-device = ðernet0;
+ };
+
+ chosen {
+ stdout-path = "serial0:38400n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ speed {
+ label = "speed";
+ gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+ };
+
+ gpio_fan_sys {
+ compatible = "gpio-fan";
+ alarm-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio_fan_psu_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&disable_jtag>;
+ compatible = "gpio-fan";
+
+ alarm-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ /* the actual speeds (rpm) are unknown, just use dummy values */
+ gpio-fan,speed-map = <1 0>, <2 1>;
+ #cooling-cells = <2>;
+ };
+
+ gpio_fan_psu_2 {
+ /* This fan runs in parallel to PSU1 fan, but has a separate
+ * alarm GPIO. This is not (yet) supported by the gpio-fan driver,
+ * so a separate instance is added
+ */
+ compatible = "gpio-fan";
+ alarm-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "green:speed";
+ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led-1 {
+ label = "green:poe";
+ gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led_sys: led-2 {
+ label = "green:sys";
+ gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led-3 {
+ label = "green:fan";
+ gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led-4 {
+ label = "amber:fan";
+ gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = "fault-fan";
+ };
+
+ led-5 {
+ label = "green:poe-max";
+ gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = "alarm-poe";
+ };
+ };
+
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* LAN9 - LAN12 */
+ tps23861@5 {
+ compatible = "ti,tps23861";
+ reg = <0x05>;
+ };
+
+ /* LAN17 - LAN20 */
+ tps23861@6 {
+ compatible = "ti,tps23861";
+ reg = <0x06>;
+ };
+
+ /* LAN45 - LAN48 */
+ tps23861@9 {
+ compatible = "ti,tps23861";
+ reg = <0x09>;
+ };
+
+ /* LAN37 - LAN40 */
+ tps23861@a {
+ compatible = "ti,tps23861";
+ reg = <0x0a>;
+ };
+
+ /* LAN1 - LAN4 */
+ tps23861@14 {
+ compatible = "ti,tps23861";
+ reg = <0x14>;
+ };
+
+ /* LAN25 - LAN28 */
+ tps23861@24 {
+ compatible = "ti,tps23861";
+ reg = <0x24>;
+ };
+
+ /* LAN33 - LAN 36 */
+ tps23861@25 {
+ compatible = "ti,tps23861";
+ reg = <0x25>;
+ };
+
+ /* LAN41 - LAN44 */
+ tps23861@26 {
+ compatible = "ti,tps23861";
+ reg = <0x26>;
+ };
+
+ /* LAN13 - LAN16 */
+ tps23861@29 {
+ compatible = "ti,tps23861";
+ reg = <0x29>;
+ };
+
+ /* LAN29 - LAN32 */
+ tps23861@2c {
+ compatible = "ti,tps23861";
+ reg = <0x2c>;
+ };
+
+ /* LAN5 - LAN8 */
+ tps23861@48 {
+ compatible = "ti,tps23861";
+ reg = <0x48>;
+ };
+
+ /* LAN21 - LAN24 */
+ tps23861@49 {
+ compatible = "ti,tps23861";
+ reg = <0x49>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&gpio0 {
+ poe-enable {
+ gpio-hog;
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "poe-enable";
+ };
+};
+
+&spi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0xe0000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0xe0000 0x20000>;
+ };
+
+ /* We use the "sys", "usrimg1" and "usrimg2" partitions
+ * as firmware since the kernel needs to be in "sys", but the
+ * partition is too small to hold the "rootfs" as well.
+ * The original partition map contains:
+ *
+ * partition@100000 {
+ * label = "sys";
+ * reg = <0x100000 0x600000>;
+ * };
+ * partition@700000 {
+ * label = "usrimg1";
+ * reg = <0x700000 0xa00000>;
+ * };
+ * partition@1100000 {
+ * label = "usrimg2";
+ * reg = <0x1100000 0xa00000>;
+ * };
+ */
+
+ partition@100000 {
+ label = "firmware";
+ reg = <0x100000 0x1a00000>;
+ };
+ partition@1b00000 {
+ label = "usrappfs";
+ reg = <0x1b00000 0x400000>;
+ };
+ partition@1f00000 {
+ label = "para";
+ reg = <0x1f00000 0x100000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ factory_macaddr: macaddr@fdff4 {
+ reg = <0xfdff4 0x6>;
+ };
+ };
+ };
+ };
+ };
+};
+
+ðernet0 {
+ nvmem-cells = <&factory_macaddr>;
+ nvmem-cell-names = "mac-address";
+
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* External phy RTL8218B #1 */
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ /* External phy RTL8218B #2 */
+ EXTERNAL_PHY(8)
+ EXTERNAL_PHY(9)
+ EXTERNAL_PHY(10)
+ EXTERNAL_PHY(11)
+ EXTERNAL_PHY(12)
+ EXTERNAL_PHY(13)
+ EXTERNAL_PHY(14)
+ EXTERNAL_PHY(15)
+
+ /* External phy RTL8218B #3 */
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ /* External phy RTL8218B #4 */
+ EXTERNAL_PHY(24)
+ EXTERNAL_PHY(25)
+ EXTERNAL_PHY(26)
+ EXTERNAL_PHY(27)
+ EXTERNAL_PHY(28)
+ EXTERNAL_PHY(29)
+ EXTERNAL_PHY(30)
+ EXTERNAL_PHY(31)
+
+ /* External phy RTL8218B #5 */
+ EXTERNAL_PHY(32)
+ EXTERNAL_PHY(33)
+ EXTERNAL_PHY(34)
+ EXTERNAL_PHY(35)
+ EXTERNAL_PHY(36)
+ EXTERNAL_PHY(37)
+ EXTERNAL_PHY(38)
+ EXTERNAL_PHY(39)
+
+ /* External phy RTL8218B #6 */
+ EXTERNAL_PHY(40)
+ EXTERNAL_PHY(41)
+ EXTERNAL_PHY(42)
+ EXTERNAL_PHY(43)
+ EXTERNAL_PHY(44)
+ EXTERNAL_PHY(45)
+ EXTERNAL_PHY(46)
+ EXTERNAL_PHY(47)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 01, qsgmii)
+ SWITCH_PORT(1, 02, qsgmii)
+ SWITCH_PORT(2, 03, qsgmii)
+ SWITCH_PORT(3, 04, qsgmii)
+ SWITCH_PORT(4, 05, qsgmii)
+ SWITCH_PORT(5, 06, qsgmii)
+ SWITCH_PORT(6, 07, qsgmii)
+ SWITCH_PORT(7, 08, qsgmii)
+
+ SWITCH_PORT(8, 09, qsgmii)
+ SWITCH_PORT(9, 10, qsgmii)
+ SWITCH_PORT(10, 11, qsgmii)
+ SWITCH_PORT(11, 12, qsgmii)
+ SWITCH_PORT(12, 13, qsgmii)
+ SWITCH_PORT(13, 14, qsgmii)
+ SWITCH_PORT(14, 15, qsgmii)
+ SWITCH_PORT(15, 16, qsgmii)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ SWITCH_PORT(24, 25, qsgmii)
+ SWITCH_PORT(25, 26, qsgmii)
+ SWITCH_PORT(26, 27, qsgmii)
+ SWITCH_PORT(27, 28, qsgmii)
+ SWITCH_PORT(28, 29, qsgmii)
+ SWITCH_PORT(29, 30, qsgmii)
+ SWITCH_PORT(30, 31, qsgmii)
+ SWITCH_PORT(31, 32, qsgmii)
+
+ SWITCH_PORT(32, 33, qsgmii)
+ SWITCH_PORT(33, 34, qsgmii)
+ SWITCH_PORT(34, 35, qsgmii)
+ SWITCH_PORT(35, 36, qsgmii)
+ SWITCH_PORT(36, 37, qsgmii)
+ SWITCH_PORT(37, 38, qsgmii)
+ SWITCH_PORT(38, 39, qsgmii)
+ SWITCH_PORT(39, 40, qsgmii)
+
+ SWITCH_PORT(40, 41, qsgmii)
+ SWITCH_PORT(41, 42, qsgmii)
+ SWITCH_PORT(42, 43, qsgmii)
+ SWITCH_PORT(43, 44, qsgmii)
+ SWITCH_PORT(44, 45, qsgmii)
+ SWITCH_PORT(45, 46, qsgmii)
+ SWITCH_PORT(46, 47, qsgmii)
+ SWITCH_PORT(47, 48, qsgmii)
+
+ /* CPU-Port */
+ port@52 {
+ ethernet = <ðernet0>;
+ reg = <52>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+/dts-v1/;
+
+#include "rtl839x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "zyxel,gs1900-48", "realtek,rtl8393-soc";
+ model = "Zyxel GS1900-48";
+
+ aliases {
+ led-boot = &led_sys;
+ led-failsafe = &led_sys;
+ led-running = &led_sys;
+ led-upgrade = &led_sys;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+ compatible = "gpio-leds";
+
+ led_sys: sys {
+ label = "green:sys";
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ indirect-access-bus-id = <3>;
+ gpio-controller;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ mode {
+ label = "reset";
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ /* i2c of the left SFP cage: port 49 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p9 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* i2c of the right SFP cage: port 50 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p10 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+ partition@50000 {
+ label = "u-boot-env2";
+ reg = <0x50000 0x10000>;
+ read-only;
+ };
+ partition@60000 {
+ label = "jffs";
+ reg = <0x60000 0x100000>;
+ };
+ partition@160000 {
+ label = "jffs2";
+ reg = <0x160000 0x100000>;
+ };
+ partition@260000 {
+ label = "firmware";
+ reg = <0x260000 0x6d0000>;
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x83800000>;
+ };
+ partition@930000 {
+ label = "runtime2";
+ reg = <0x930000 0x6d0000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* External phy RTL8218B #1 */
+ EXTERNAL_PHY(0)
+ EXTERNAL_PHY(1)
+ EXTERNAL_PHY(2)
+ EXTERNAL_PHY(3)
+ EXTERNAL_PHY(4)
+ EXTERNAL_PHY(5)
+ EXTERNAL_PHY(6)
+ EXTERNAL_PHY(7)
+
+ /* External phy RTL8218B #2 */
+ EXTERNAL_PHY(8)
+ EXTERNAL_PHY(9)
+ EXTERNAL_PHY(10)
+ EXTERNAL_PHY(11)
+ EXTERNAL_PHY(12)
+ EXTERNAL_PHY(13)
+ EXTERNAL_PHY(14)
+ EXTERNAL_PHY(15)
+
+ /* External phy RTL8218B #3 */
+ EXTERNAL_PHY(16)
+ EXTERNAL_PHY(17)
+ EXTERNAL_PHY(18)
+ EXTERNAL_PHY(19)
+ EXTERNAL_PHY(20)
+ EXTERNAL_PHY(21)
+ EXTERNAL_PHY(22)
+ EXTERNAL_PHY(23)
+
+ /* External phy RTL8218B #4 */
+ EXTERNAL_PHY(24)
+ EXTERNAL_PHY(25)
+ EXTERNAL_PHY(26)
+ EXTERNAL_PHY(27)
+ EXTERNAL_PHY(28)
+ EXTERNAL_PHY(29)
+ EXTERNAL_PHY(30)
+ EXTERNAL_PHY(31)
+
+ /* External phy RTL8218B #5 */
+ EXTERNAL_PHY(32)
+ EXTERNAL_PHY(33)
+ EXTERNAL_PHY(34)
+ EXTERNAL_PHY(35)
+ EXTERNAL_PHY(36)
+ EXTERNAL_PHY(37)
+ EXTERNAL_PHY(38)
+ EXTERNAL_PHY(39)
+
+ /* External phy RTL8218B #6 */
+ EXTERNAL_PHY(40)
+ EXTERNAL_PHY(41)
+ EXTERNAL_PHY(42)
+ EXTERNAL_PHY(43)
+ EXTERNAL_PHY(44)
+ EXTERNAL_PHY(45)
+ EXTERNAL_PHY(46)
+ EXTERNAL_PHY(47)
+
+ /* RTL8393 Internal SerDes */
+ INTERNAL_PHY(48)
+ INTERNAL_PHY(49)
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ SWITCH_PORT(0, 01, qsgmii)
+ SWITCH_PORT(1, 02, qsgmii)
+ SWITCH_PORT(2, 03, qsgmii)
+ SWITCH_PORT(3, 04, qsgmii)
+ SWITCH_PORT(4, 05, qsgmii)
+ SWITCH_PORT(5, 06, qsgmii)
+ SWITCH_PORT(6, 07, qsgmii)
+ SWITCH_PORT(7, 08, qsgmii)
+
+ SWITCH_PORT(8, 09, qsgmii)
+ SWITCH_PORT(9, 10, qsgmii)
+ SWITCH_PORT(10, 11, qsgmii)
+ SWITCH_PORT(11, 12, qsgmii)
+ SWITCH_PORT(12, 13, qsgmii)
+ SWITCH_PORT(13, 14, qsgmii)
+ SWITCH_PORT(14, 15, qsgmii)
+ SWITCH_PORT(15, 16, qsgmii)
+
+ SWITCH_PORT(16, 17, qsgmii)
+ SWITCH_PORT(17, 18, qsgmii)
+ SWITCH_PORT(18, 19, qsgmii)
+ SWITCH_PORT(19, 20, qsgmii)
+ SWITCH_PORT(20, 21, qsgmii)
+ SWITCH_PORT(21, 22, qsgmii)
+ SWITCH_PORT(22, 23, qsgmii)
+ SWITCH_PORT(23, 24, qsgmii)
+
+ SWITCH_PORT(24, 25, qsgmii)
+ SWITCH_PORT(25, 26, qsgmii)
+ SWITCH_PORT(26, 27, qsgmii)
+ SWITCH_PORT(27, 28, qsgmii)
+ SWITCH_PORT(28, 29, qsgmii)
+ SWITCH_PORT(29, 30, qsgmii)
+ SWITCH_PORT(30, 31, qsgmii)
+ SWITCH_PORT(31, 32, qsgmii)
+
+ SWITCH_PORT(32, 33, qsgmii)
+ SWITCH_PORT(33, 34, qsgmii)
+ SWITCH_PORT(34, 35, qsgmii)
+ SWITCH_PORT(35, 36, qsgmii)
+ SWITCH_PORT(36, 37, qsgmii)
+ SWITCH_PORT(37, 38, qsgmii)
+ SWITCH_PORT(38, 39, qsgmii)
+ SWITCH_PORT(39, 40, qsgmii)
+
+ SWITCH_PORT(40, 41, qsgmii)
+ SWITCH_PORT(41, 42, qsgmii)
+ SWITCH_PORT(42, 43, qsgmii)
+ SWITCH_PORT(43, 44, qsgmii)
+ SWITCH_PORT(44, 45, qsgmii)
+ SWITCH_PORT(45, 46, qsgmii)
+ SWITCH_PORT(46, 47, qsgmii)
+ SWITCH_PORT(47, 48, qsgmii)
+
+ /* SFP cages */
+ port@48 {
+ reg = <48>;
+ label = "lan49";
+ phy-mode = "sgmii";
+ phy-handle = <&phy48>;
+ sfp = <&sfp0>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+
+ };
+
+ port@49 {
+ reg = <49>;
+ label = "lan50";
+ phy-mode = "sgmii";
+ phy-handle = <&phy49>;
+ sfp = <&sfp1>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+
+ };
+
+ /* CPU-Port */
+ port@52 {
+ ethernet = <ðernet0>;
+ reg = <52>;
+ phy-mode = "qsgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/clock/rtl83xx-clk.h>
+
+/dts-v1/;
+
+#define STRINGIZE(s) #s
+#define LAN_LABEL(p, s) STRINGIZE(p ## s)
+#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
+
+#define INTERNAL_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ reg = <##n>; \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ phy-is-integrated; \
+ };
+
+#define EXTERNAL_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ reg = <##n>; \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ };
+
+#define EXTERNAL_SFP_PHY(n) \
+ phy##n: ethernet-phy@##n { \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ sfp; \
+ media = "fibre"; \
+ reg = <##n>; \
+ };
+
+#define EXTERNAL_SFP_PHY_FULL(n, s) \
+ phy##n: ethernet-phy@##n { \
+ compatible = "ethernet-phy-ieee802.3-c22"; \
+ sfp = <&sfp##s>; \
+ reg = <##n>; \
+ };
+
+#define SWITCH_PORT(n, s, m) \
+ port@##n { \
+ reg = <##n>; \
+ label = SWITCH_PORT_LABEL(s) ; \
+ phy-handle = <&phy##n>; \
+ phy-mode = #m ; \
+ };
+
+#define SWITCH_SFP_PORT(n, s, m) \
+ port@##n { \
+ reg = <##n>; \
+ label = SWITCH_PORT_LABEL(s) ; \
+ phy-handle = <&phy##n>; \
+ phy-mode = #m ; \
+ fixed-link { \
+ speed = <1000>; \
+ full-duplex; \
+ }; \
+ };
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "realtek,rtl839x-soc";
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ ccu: clock-controller {
+ compatible = "realtek,rtl8390-clock";
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ clock-names = "ref_clk";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips34Kc";
+ reg = <0>;
+ clocks = <&ccu CLK_CPU>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+ cpu@1 {
+ compatible = "mips,mips34Kc";
+ reg = <1>;
+ clocks = <&ccu CLK_CPU>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+
+ cpu_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <425000000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <450000000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <475000000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <500000000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <525000000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <550000000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <575000000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <600000000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <625000000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <650000000>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <675000000>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <700000000>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <725000000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpuintc: cpuintc {
+ compatible = "mti,cpu-interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000000 0x10000>;
+
+ intc: interrupt-controller@3000 {
+ compatible = "realtek,rtl8390-intc", "realtek,rtl-intc";
+ reg = <0x3000 0x18>, <0x3018 0x18>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>, <4>, <5>, <6>;
+ };
+
+ spi0: spi@1200 {
+ compatible = "realtek,rtl8380-spi";
+ reg = <0x1200 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer0: timer@3100 {
+ compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
+ reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
+ <0x3130 0x10>, <0x3140 0x10>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
+ clocks = <&ccu CLK_LXB>;
+ };
+
+ uart0: uart@2000 {
+ compatible = "ns16550a";
+ reg = <0x2000 0x100>;
+
+ clocks = <&ccu CLK_LXB>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <31 1>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+ };
+
+ uart1: uart@2100 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&enable_uart1>;
+
+ compatible = "ns16550a";
+ reg = <0x2100 0x100>;
+
+ clocks = <&ccu CLK_LXB>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30 2>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@3500 {
+ compatible = "realtek,rtl8390-gpio", "realtek,otto-gpio";
+ reg = <0x3500 0x20>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <24>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <23 2>;
+ };
+
+ watchdog0: watchdog@3150 {
+ compatible = "realtek,rtl8390-wdt";
+ reg = <0x3150 0xc>;
+
+ realtek,reset-mode = "soc";
+
+ clocks = <&ccu CLK_LXB>;
+ timeout-sec = <30>;
+
+ interrupt-parent = <&intc>;
+ interrupt-names = "phase1", "phase2";
+ interrupts = <19 4>, <18 4>;
+ };
+
+ };
+
+ pinmux@1b000004 {
+ compatible = "pinctrl-single";
+ reg = <0x1b000004 0x4>;
+
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x1>;
+ #pinctrl-cells = <2>;
+
+ enable_uart1: pinmux_enable_uart1 {
+ pinctrl-single,bits = <0x0 0x1 0x3>;
+ };
+
+ disable_jtag: pinmux_disable_jtag {
+ pinctrl-single,bits = <0x0 0x2 0x3>;
+ };
+ };
+
+ /* LED_GLB_CTRL */
+ pinmux@1b0000e4 {
+ compatible = "pinctrl-single";
+ reg = <0x1b0000e4 0x4>;
+
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x1>;
+ #pinctrl-cells = <2>;
+
+ /* enable GPIO 0 */
+ pinmux_disable_sys_led: disable_sys_led {
+ pinctrl-single,bits = <0x0 0x0 0x4000>;
+ };
+ };
+
+ ethernet0: ethernet@1b00a300 {
+ compatible = "realtek,rtl838x-eth";
+ reg = <0x1b00a300 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <24 3>;
+
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ sram0: sram@9f000000 {
+ compatible = "mmio-sram";
+ reg = <0x9f000000 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x9f000000 0x18000>;
+ };
+
+ switch0: switch@1b000000 {
+ status = "okay";
+ compatible = "realtek,rtl83xx-switch";
+
+ interrupt-parent = <&intc>;
+ interrupts = <20 2>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/ {
+ /* Lan 49 */
+ i2c0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp0: sfp-p49 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ /* tx-disable-gpio handled by RTL8214FC based on media setting */
+ };
+
+ /* Lan 50 */
+ i2c1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp-p50 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c1>;
+ los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ /* tx-disable-gpio handled by RTL8214FC based on media setting */
+ };
+
+ /* Lan 51 */
+ i2c2: i2c-gpio-2 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp2: sfp-p51 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c2>;
+ los-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>;
+ /* tx-disable-gpio handled by RTL8214FC based on media setting */
+ };
+
+ /* Lan 52 */
+ i2c3: i2c-gpio-3 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp3: sfp-p52 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c3>;
+ los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ /* tx-disable-gpio handled by RTL8214FC based on media setting */
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ leds: leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+ compatible = "gpio-leds";
+
+ led_power: power {
+ label = "green:power";
+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&gpio0 {
+ indirect-access-bus-id = <0>;
+};
+
+&spi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x80000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x00080000 0x40000>;
+ };
+ partition@c0000 {
+ label = "board-name";
+ reg = <0x000c0000 0x40000>;
+ };
+ partition@280000 {
+ label = "firmware";
+ compatible = "denx,uimage";
+ reg = <0x00100000 0xd80000>;
+ };
+ partition@be80000 {
+ label = "kernel2";
+ reg = <0x00e80000 0x180000>;
+ };
+ partition@1000000 {
+ label = "sysinfo";
+ reg = <0x01000000 0x40000>;
+ };
+ partition@1040000 {
+ label = "rootfs2";
+ reg = <0x01040000 0xc00000>;
+ };
+ partition@1c40000 {
+ label = "jffs2";
+ reg = <0x01c40000 0x3c0000>;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/ {
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
+ open-source;
+ };
+
+ keys: keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <20>;
+
+ reset {
+ label = "reset";
+ gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio1: rtl8231-gpio {
+ compatible = "realtek,rtl8231-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ indirect-access-bus-id = <0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ leds: leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "amber:any_col";
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_FAULT;
+ };
+
+ led-1 {
+ label = "green:giga";
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <1>;
+ };
+
+ led-2 {
+ label = "green:100m";
+ gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <2>;
+ };
+
+ led-3 {
+ label = "green:full";
+ gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <3>;
+ };
+
+ led-4 {
+ label = "green:loop_history";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ function-enumerator = <4>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ led_mode {
+ label = "led-mode";
+ gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ i2c_gpio_0: i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio1: gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio2: gpio@75 {
+ compatible = "nxp,pca9539";
+ reg = <0x75>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ /*
+ * GPIO14 (IO1_6): Shift Register RESET (port LED)
+ * - Switch-M8eG PN28080K: 3x 74HC164
+ * - Switch-M16eG PN28160K: 4x 74HC164
+ * - Switch-M24eG PN28240K: 6x 74HC164
+ * - Switch-M48eG PN28480K: 12x 74HC164
+ */
+ portled_sregister_reset {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "portled-sregister-reset";
+ };
+ };
+ };
+
+ i2c_gpio_1: i2c-gpio-1 {
+ compatible = "i2c-gpio";
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c_switch: i2c-switch@70 {
+ compatible = "nxp,pca9545";
+ reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x80000 0x10000>;
+ };
+
+ partition@90000 {
+ label = "u-boot-env2";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@a0000 {
+ label = "sysinfo";
+ reg = <0xa0000 0x60000>;
+ read-only;
+ };
+
+ /*
+ * Filesystem area in stock firmware
+ * (0x100000-0x1DFFFFF)
+ *
+ * stock firmware images are required to pass
+ * the checking by the U-Boot, also for OpenWrt
+ *
+ * in OpenWrt:
+ * - 0x100000-0xDFFFFF (13M): stock images
+ * - 0xE00000-0x1DFFFFF(16M): OpenWrt image
+ */
+ partition@100000 {
+ label = "fs_reserved";
+ reg = <0x100000 0xd00000>;
+ };
+
+ partition@e00000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0xe00000 0x1000000>;
+ };
+
+ partition@1e00000 {
+ label = "vlog_data";
+ reg = <0x1e00000 0x100000>;
+ read-only;
+ };
+
+ partition@1f00000 {
+ label = "elog_data";
+ reg = <0x1f00000 0x100000>;
+ read-only;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/dts-v1/;
+
+#include "rtl930x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "zyxel,xgs1250-12", "realtek,rtl838x-soc";
+ model = "Zyxel XGS1250-12 Switch";
+
+ aliases {
+ led-boot = &led_pwr_sys;
+ led-failsafe = &led_pwr_sys;
+ led-running = &led_pwr_sys;
+ led-upgrade = &led_pwr_sys;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ mode {
+ label = "reset";
+ gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ /* i2c of the SFP cage: port 12 */
+ i2c0: i2c-rtl9300@1b00036c {
+ compatible = "realtek,rtl9300-i2c";
+ reg = <0x1b00036c 0x3c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sda-pin = <10>;
+ scl-pin = <8>;
+ clock-frequency = <100000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_disable_sys_led>;
+
+ led_pwr_sys: led-0 {
+ label = "green:power";
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ sfp0: sfp-p12 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c0>;
+ los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_set: led_set {
+ compatible = "realtek,rtl9300-leds";
+ active-low;
+
+ led_set0 = <0x0a20 0x0b80>; // LED set 0: 1000Mbps, 10/100Mbps
+ led_set1 = <0x0a0b 0x0a28 0x0a82 0x0a0b>; // LED set 1: (10G, 5G, 2.5G) (2.5G, 1G)
+ // (5G, 10/100) (10G, 5G, 2.5G)
+ led_set2 = <0x0a20 0x0a01>; // LED set 2: 1000MBit, 10GBit
+ };
+};
+
+&spi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0xe0000>;
+ read-only;
+ };
+ partition@e0000 {
+ label = "u-boot-env";
+ reg = <0xe0000 0x10000>;
+ };
+ partition@f0000 {
+ label = "u-boot-env2";
+ reg = <0xf0000 0x10000>;
+ read-only;
+ };
+ partition@100000 {
+ label = "jffs";
+ reg = <0x100000 0x100000>;
+ };
+ partition@200000 {
+ label = "jffs2";
+ reg = <0x200000 0x100000>;
+ };
+ partition@b300000 {
+ label = "firmware";
+ reg = <0x300000 0xce0000>;
+ compatible = "openwrt,uimage", "denx,uimage";
+ openwrt,ih-magic = <0x93001250>;
+ };
+ partition@fe0000 {
+ label = "log";
+ reg = <0xfe0000 0x20000>;
+ };
+ };
+ };
+};
+
+ðernet0 {
+ mdio: mdio-bus {
+ compatible = "realtek,rtl838x-mdio";
+ regmap = <ðernet0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* External RTL8218D PHY */
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 0>;
+ sds = < 2 >;
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ rtl9300,smi-address = <0 7>;
+ };
+
+ /* External Aquantia 113C PHYs */
+ phy24: ethernet-phy@24 {
+ reg = <24>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rtl9300,smi-address = <1 8>;
+ sds = < 6 >;
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ phy25: ethernet-phy@25 {
+ reg = <25>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rtl9300,smi-address = <2 8>;
+ sds = < 7 >;
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ phy26: ethernet-phy@26 {
+ reg = <26>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ rtl9300,smi-address = <3 8>;
+ sds = < 8 >;
+ // Disabled because we do not know how to bring up again
+ // reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ /* SFP Ports */
+ phy27: ethernet-phy@27 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ phy-is-integrated;
+ reg = <27>;
+ rtl9300,smi-address = <4 0>;
+ sds = < 9 >;
+ };
+
+ };
+};
+
+&switch0 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-handle = <&phy0>;
+ phy-mode = "xgmii";
+ led-set = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-handle = <&phy1>;
+ phy-mode = "xgmii";
+ led-set = <0>;
+ };
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-handle = <&phy2>;
+ phy-mode = "xgmii";
+ led-set = <0>;
+ };
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-handle = <&phy3>;
+ phy-mode = "xgmii";
+ led-set = <0>;
+ };
+ port@4 {
+ reg = <4>;
+ label = "lan5";
+ phy-handle = <&phy4>;
+ phy-mode = "xgmii";
+ led-set = <0>;
+ };
+ port@5 {
+ reg = <5>;
+ label = "lan6";
+ phy-handle = <&phy5>;
+ phy-mode = "xgmii";
+ led-set = <0>;
+ };
+ port@6 {
+ reg = <6>;
+ label = "lan7";
+ phy-handle = <&phy6>;
+ phy-mode = "xgmii";
+ led-set = <0>;
+ };
+ port@7 {
+ reg = <7>;
+ label = "lan8";
+ phy-handle = <&phy7>;
+ phy-mode = "xgmii";
+ led-set = <0>;
+ };
+
+ port@24 {
+ reg = <24>;
+ label = "lan9";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy24>;
+ led-set = <1>;
+ };
+ port@25 {
+ reg = <25>;
+ label = "lan10";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy25>;
+ led-set = <1>;
+ };
+ port@26 {
+ reg = <26>;
+ label = "lan11";
+ phy-mode = "usxgmii";
+ phy-handle = <&phy26>;
+ led-set = <1>;
+ };
+
+ port@27 {
+ reg = <27>;
+ label = "lan12";
+ phy-mode = "10gbase-r";
+ phy-handle = <&phy27>;
+ sfp = <&sfp0>;
+ led-set = <2>;
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+
+ };
+
+ port@28 {
+ ethernet = <ðernet0>;
+ reg = <28>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "realtek,rtl838x-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ frequency = <800000000>;
+
+ cpu@0 {
+ compatible = "mips,mips34Kc";
+ reg = <0>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x8000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpuintc: cpuintc {
+ compatible = "mti,cpu-interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ lx_clk: lx_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <175000000>;
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000000 0x10000>;
+
+ intc: interrupt-controller@3000 {
+ compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
+ reg = <0x3000 0x18>, <0x3018 0x18>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
+ };
+
+ spi0: spi@1200 {
+ compatible = "realtek,rtl8380-spi";
+ reg = <0x1200 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer0: timer@3200 {
+ compatible = "realtek,rtl930x-timer", "realtek,otto-timer";
+ reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
+ <0x3230 0x10>, <0x3240 0x10>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <7 4>, <8 4>, <9 4>, <10 4>, <11 4>;
+ clocks = <&lx_clk>;
+ };
+
+ uart0: uart@2000 {
+ compatible = "ns16550a";
+ reg = <0x2000 0x100>;
+
+ clocks = <&lx_clk>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30 1>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+ };
+
+ uart1: uart@2100 {
+ compatible = "ns16550a";
+ reg = <0x2100 0x100>;
+
+ clocks = <&lx_clk>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <31 0>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@3260 {
+ compatible = "realtek,rtl9300-wdt";
+ reg = <0x3260 0xc>;
+
+ realtek,reset-mode = "soc";
+
+ clocks = <&lx_clk>;
+ timeout-sec = <30>;
+
+ interrupt-parent = <&intc>;
+ interrupt-names = "phase1", "phase2";
+ interrupts = <5 4>, <6 4>;
+ };
+
+ gpio0: gpio-controller@3300 {
+ compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
+ reg = <0x3300 0x1c>, <0x3338 0x8>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <24>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <13 1>;
+ };
+
+ };
+
+ pinmux_led: pinmux@1b00cc00 {
+ compatible = "pinctrl-single";
+ reg = <0x1b00cc00 0x4>;
+
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x1>;
+ #pinctrl-cells = <2>;
+
+ /* enable GPIO 0 */
+ pinmux_disable_sys_led: disable_sys_led {
+ pinctrl-single,bits = <0x0 0x0 0x1000>;
+ };
+ };
+
+ ethernet0: ethernet@1b00a300 {
+ compatible = "realtek,rtl838x-eth";
+ reg = <0x1b00a300 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <24 3>;
+
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ switch0: switch@1b000000 {
+ compatible = "realtek,rtl83xx-switch";
+ status = "okay";
+
+ interrupt-parent = <&intc>;
+ interrupts = <23 2>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "realtek,rtl838x-soc";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ frequency = <1000000000>;
+
+ cpu@0 {
+ compatible = "mti,interaptive";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "mti,interaptive";
+ reg = <1>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ lx_clk: lx_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ cpuclock: cpuclock@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+
+ /* FIXME: there should be way to detect this */
+ clock-frequency = <1000000000>;
+ };
+
+ cpuintc: cpuintc {
+ compatible = "mti,cpu-interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ gic: interrupt-controller@1ddc0000 {
+ compatible = "mti,gic";
+ reg = <0x1ddc0000 0x20000>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ /*
+ * Declare the interrupt-parent even though the mti,gic
+ * binding doesn't require it, such that the kernel can
+ * figure out that cpu_intc is the root interrupt
+ * controller & should be probed first.
+ */
+ interrupt-parent = <&cpuintc>;
+
+ timer {
+ compatible = "mti,gic-timer";
+ interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+ clocks = <&cpuclock>;
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x18000000 0x10000>;
+
+ spi0: spi@1200 {
+ status = "okay";
+
+ compatible = "realtek,rtl8380-spi";
+ reg = <0x1200 0x100>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ watchdog0: watchdog@3260 {
+ compatible = "realtek,rtl9310-wdt";
+ reg = <0x3260 0xc>;
+
+ realtek,reset-mode = "soc";
+
+ clocks = <&lx_clk>;
+ timeout-sec = <30>;
+
+ interrupt-parent = <&gic>;
+ interrupt-names = "phase1", "phase2";
+ interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SHARED 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gpio0: gpio-controller@3300 {
+ compatible = "realtek,rtl9310-gpio", "realtek,otto-gpio";
+ reg = <0x3300 0x1c>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ uart0: uart@2000 {
+ compatible = "ns16550a";
+ reg = <0x2000 0x100>;
+
+ clock-frequency = <200000000>;
+
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+ };
+
+ uart1: uart@2100 {
+ compatible = "ns16550a";
+ reg = <0x2100 0x100>;
+
+ clock-frequency = <200000000>;
+
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg-io-width = <1>;
+ reg-shift = <2>;
+ fifo-size = <1>;
+ no-loopback-test;
+
+ status = "disabled";
+ };
+ };
+
+ pinmux: pinmux@1b001358 {
+ compatible = "pinctrl-single";
+ reg = <0x1b001358 0x4>;
+
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x1>;
+ #pinctrl-cells = <2>;
+
+ /* Enable GPIO6 and GPIO7, possibly unknown others */
+ pinmux_disable_jtag: disable_jtag {
+ pinctrl-single,bits = <0x0 0x0 0x8000>;
+ };
+
+ /* Controls GPIO0 */
+ pinmux_disable_sys_led: disable_sys_led {
+ pinctrl-single,bits = <0x0 0x0 0x100>;
+ };
+ };
+
+ ethernet0: ethernet@1b00a300 {
+ status = "okay";
+ compatible = "realtek,rtl838x-eth";
+ reg = <0x1b00a300 0x100>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
+ phy-mode = "internal";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ switch0: switch@1b000000 {
+ compatible = "realtek,rtl83xx-switch";
+ status = "okay";
+
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SHARED 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
append-dtb | \
libdeflate-gzip | \
uImage gzip
- DEVICE_DTS_DIR := ../dts-$(KERNEL_PATCHVER)
+ DEVICE_DTS_DIR := ../dts
DEVICE_DTS = $$(SOC)_$(1)
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := \
projects / openwrt / staging / svanheule.git / commitdiff