drm/i915/bxt: Add GEN8_L3SQCREG4 to HW whitelist

Required for WaDisableLSQCROPERFforOCL:bxt

According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares the same GT these are extended for A1 as well.

This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.

v2: explain purpose of changes (Chris)

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-6-git-send-email-arun.siluvery@linux.intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index a99f8340fb479af1db0d7d224fbb002a23ec99f5..12eb1e0f786b530c31a82b6bf190a7dde613d556 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1136,10 +1136,15 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
        /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
        /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
        /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
+       /* WaDisableLSQCROPERFforOCL:bxt */
        if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
                ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1);
                if (ret)
                        return ret;
+
+               ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4);
+               if (ret)
+                       return ret;
        }
 
        return 0;