val, AR71XX_ETH1_PLL_SHIFT);
}
+static void ar724x_set_pll_ge0(int speed)
+{
+ /* TODO */
+}
+
+static void ar724x_set_pll_ge1(int speed)
+{
+ /* TODO */
+}
+
static void ar91xx_set_pll_ge0(int speed)
{
u32 val = ar71xx_get_eth_pll(0, speed);
ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
}
+static void ar724x_ddr_flush_ge0(void)
+{
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
+}
+
+static void ar724x_ddr_flush_ge1(void)
+{
+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
+}
+
static void ar91xx_ddr_flush_ge0(void)
{
ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
#define AR71XX_PLL_VAL_100 0x00001099
#define AR71XX_PLL_VAL_10 0x00991099
+#define AR724X_PLL_VAL_1000 0x00110000
+#define AR724X_PLL_VAL_100 0x00001099
+#define AR724X_PLL_VAL_10 0x00991099
+
#define AR91XX_PLL_VAL_1000 0x1a000000
#define AR91XX_PLL_VAL_100 0x13000a44
#define AR91XX_PLL_VAL_10 0x00441099
pll_100 = AR71XX_PLL_VAL_100;
pll_1000 = AR71XX_PLL_VAL_1000;
break;
+
+ case AR71XX_SOC_AR7240:
+ pll_10 = AR724X_PLL_VAL_10;
+ pll_100 = AR724X_PLL_VAL_100;
+ pll_1000 = AR724X_PLL_VAL_1000;
+ break;
+
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
pll_10 = AR91XX_PLL_VAL_10;
pdata->has_gbit = 1;
break;
+ case AR71XX_SOC_AR7240:
+ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
+ : ar724x_ddr_flush_ge0;
+ pdata->set_pll = id ? ar724x_set_pll_ge1
+ : ar724x_set_pll_ge0;
+ pdata->is_ar724x = 1;
+ break;
+
case AR71XX_SOC_AR9130:
pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
: ar91xx_ddr_flush_ge0;
static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+ if (pdata->is_ar724x)
+ return;
+
__raw_writel(value, ag->mii_ctrl);
__raw_readl(ag->mii_ctrl);
}
static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+
+ if (pdata->is_ar724x)
+ return 0xffffffff;
+
return __raw_readl(ag->mii_ctrl);
}
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3,
pdata->is_ar91xx ? 0x780fff : 0x008001ff);
- pdata->set_pll(ag->speed);
+
+ if (pdata->set_pll)
+ pdata->set_pll(ag->speed);
+
ag71xx_mii_ctrl_set_speed(ag, mii_speed);
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);