drm/i915/tgl: do not enable transcoder clock twice on MST

For MST on Tiger Lake there are different moments when we need to
configure the transcoder clock select. For the first link this is in step
7.a of the spec, before training the link.  For additional streams this
should be done as part of step 8.b after programming receiver VC Payload
ID.

Bspec: 49190

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191030012448.14937-4-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7deae472be5f81fc5ae9d1ad2ef19d6f2fb19a93..2f05110191a01ee2c9ad02baaeeb7d149ec6334c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3462,9 +3462,10 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
        icl_program_mg_dp_mode(dig_port, crtc_state);
 
        /*
-        * 7.a - Steps in this function should only be executed over MST
-        * master, what will be taken in care by MST hook
-        * intel_mst_pre_enable_dp()
+        * 7.a - single stream or multi-stream master transcoder: Configure
+        * Transcoder Clock Select. For additional MST streams this will be done
+        * by intel_mst_pre_enable_dp() after programming VC Payload ID through
+        * AUX.
         */
        intel_ddi_enable_pipe_clock(crtc_state);
 

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5b2ca81f5cd6d9537162937f50e0166ce1375d10..27494aa48b0b0885b52f9878a37b2c6af3bfe302 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -303,21 +303,23 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
                to_intel_connector(conn_state->connector);
        int ret;
        u32 temp;
+       bool first_mst_stream;
 
        /* MST encoders are bound to a crtc, not to a connector,
         * force the mapping here for get_hw_state.
         */
        connector->encoder = encoder;
        intel_mst->connector = connector;
+       first_mst_stream = intel_dp->active_mst_links == 0;
 
        DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
-       if (intel_dp->active_mst_links == 0)
+       if (first_mst_stream)
                intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
 
        drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
 
-       if (intel_dp->active_mst_links == 0)
+       if (first_mst_stream)
                intel_dig_port->base.pre_enable(&intel_dig_port->base,
                                                pipe_config, NULL);
 
@@ -334,7 +336,15 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
 
        ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
 
-       intel_ddi_enable_pipe_clock(pipe_config);
+       /*
+        * Before Gen 12 this is not done as part of
+        * intel_dig_port->base.pre_enable() and should be done here. For
+        * Gen 12+ the step in which this should be done is different for the
+        * first MST stream, so it's done on the DDI for the first stream and
+        * here for the following ones.
+        */
+       if (INTEL_GEN(dev_priv) < 12 || !first_mst_stream)
+               intel_ddi_enable_pipe_clock(pipe_config);
 }
 
 static void intel_mst_enable_dp(struct intel_encoder *encoder,