#### Platform initialization
-BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from
+BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
the CCI slave interface corresponding to the cluster that includes the
primary CPU. BL1 also initializes a UART (PL011 console), which enables access
to the `printf` family of functions in BL1.
BL3-1 performs detailed platform initialization, which enables normal world
software to function correctly. It also retrieves entrypoint information for
the BL3-3 image loaded by BL2 from the platform defined memory address populated
-by BL2. BL3-1 also initializes a UART (PL011 console), which enables
+by BL2. It enables issuing of snoop and DVM (Distributed Virtual Memory)
+requests to the CCI slave interface corresponding to the cluster that includes
+the primary CPU. BL3-1 also initializes a UART (PL011 console), which enables
access to the `printf` family of functions in BL3-1. It enables the system
level implementation of the generic timer through the memory mapped interface.
must place any secondary CPUs into a safe state while the primary CPU executes
a modified BL3-1 initialization, as described below.
-#### Architectural initialization
-
-As the first image to execute in this configuration BL3-1 must ensure that
-interconnect coherency is enabled (if required) before enabling the MMU.
-
#### Platform initialization
In this configuration, when the CPU resets to BL3-1 there are no parameters
* No need for locks as no other CPU is active.
*/
fvp_cci_init();
-#if RESET_TO_BL31
+
/*
- * Enable CCI coherency for the primary CPU's cluster
- * (if earlier BL has not already done so).
+ * Enable CCI coherency for the primary CPU's cluster.
+ * Earlier bootloader stages might already do this (e.g. Trusted
+ * Firmware's BL1 does it) but we can't assume so. There is no harm in
+ * executing this code twice anyway.
* FVP PSCI code will enable coherency for other clusters.
*/
fvp_cci_enable();
-
-#endif /* RESET_TO_BL31 */
}
* No need for locks as no other CPU is active.
*/
arm_cci_init();
-#if RESET_TO_BL31
+
/*
- * Enable CCI coherency for the primary CPU's cluster
- * (if earlier BL has not already done so).
+ * Enable CCI coherency for the primary CPU's cluster.
+ * Earlier bootloader stages might already do this (e.g. Trusted
+ * Firmware's BL1 does it) but we can't assume so. There is no harm in
+ * executing this code twice anyway.
* Platform specific PSCI code will enable coherency for other
* clusters.
*/
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
-
-#endif /* RESET_TO_BL31 */
}
/*******************************************************************************