drm/i915/icl: Icelake interrupt register addresses and bits

MMIO addresses and register definition for the new interrupt
registers in Gen11.

v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter)
v3: Adjust VCS and VECS. (Daniele Ceraolo Spurio)
v4: Bikeshedding (Paulo).

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180109232336.11029-5-paulo.r.zanoni@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1b28669f4f997b6a20288c429897eddcf6660c21..43ac9be7c7460d15876eb3a41ed86728b7d35691 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6962,6 +6962,69 @@ enum {
 #define GEN8_PCU_IIR _MMIO(0x444e8)
 #define GEN8_PCU_IER _MMIO(0x444ec)
 
+#define GEN11_GFX_MSTR_IRQ             _MMIO(0x190010)
+#define  GEN11_MASTER_IRQ              (1 << 31)
+#define  GEN11_PCU_IRQ                 (1 << 30)
+#define  GEN11_DISPLAY_IRQ             (1 << 16)
+#define  GEN11_GT_DW_IRQ(x)            (1 << (x))
+#define  GEN11_GT_DW1_IRQ              (1 << 1)
+#define  GEN11_GT_DW0_IRQ              (1 << 0)
+
+#define GEN11_DISPLAY_INT_CTL          _MMIO(0x44200)
+#define  GEN11_DISPLAY_IRQ_ENABLE      (1 << 31)
+#define  GEN11_AUDIO_CODEC_IRQ         (1 << 24)
+#define  GEN11_DE_PCH_IRQ              (1 << 23)
+#define  GEN11_DE_MISC_IRQ             (1 << 22)
+#define  GEN11_DE_PORT_IRQ             (1 << 20)
+#define  GEN11_DE_PIPE_C               (1 << 18)
+#define  GEN11_DE_PIPE_B               (1 << 17)
+#define  GEN11_DE_PIPE_A               (1 << 16)
+
+#define GEN11_GT_INTR_DW0              _MMIO(0x190018)
+#define  GEN11_CSME                    (31)
+#define  GEN11_GUNIT                   (28)
+#define  GEN11_GUC                     (25)
+#define  GEN11_WDPERF                  (20)
+#define  GEN11_KCR                     (19)
+#define  GEN11_GTPM                    (16)
+#define  GEN11_BCS                     (15)
+#define  GEN11_RCS0                    (0)
+
+#define GEN11_GT_INTR_DW1              _MMIO(0x19001c)
+#define  GEN11_VECS(x)                 (31 - (x))
+#define  GEN11_VCS(x)                  (x)
+
+#define GEN11_GT_INTR_DW(x)            _MMIO(0x190018 + (x * 4))
+
+#define GEN11_INTR_IDENTITY_REG0       _MMIO(0x190060)
+#define GEN11_INTR_IDENTITY_REG1       _MMIO(0x190064)
+#define  GEN11_INTR_DATA_VALID         (1 << 31)
+#define  GEN11_INTR_ENGINE_MASK                (0xffff)
+
+#define GEN11_INTR_IDENTITY_REG(x)     _MMIO(0x190060 + (x * 4))
+
+#define GEN11_IIR_REG0_SELECTOR                _MMIO(0x190070)
+#define GEN11_IIR_REG1_SELECTOR                _MMIO(0x190074)
+
+#define GEN11_IIR_REG_SELECTOR(x)      _MMIO(0x190070 + (x * 4))
+
+#define GEN11_RENDER_COPY_INTR_ENABLE  _MMIO(0x190030)
+#define GEN11_VCS_VECS_INTR_ENABLE     _MMIO(0x190034)
+#define GEN11_GUC_SG_INTR_ENABLE       _MMIO(0x190038)
+#define GEN11_GPM_WGBOXPERF_INTR_ENABLE        _MMIO(0x19003c)
+#define GEN11_CRYPTO_RSVD_INTR_ENABLE  _MMIO(0x190040)
+#define GEN11_GUNIT_CSME_INTR_ENABLE   _MMIO(0x190044)
+
+#define GEN11_RCS0_RSVD_INTR_MASK      _MMIO(0x190090)
+#define GEN11_BCS_RSVD_INTR_MASK       _MMIO(0x1900a0)
+#define GEN11_VCS0_VCS1_INTR_MASK      _MMIO(0x1900a8)
+#define GEN11_VCS2_VCS3_INTR_MASK      _MMIO(0x1900ac)
+#define GEN11_VECS0_VECS1_INTR_MASK    _MMIO(0x1900d0)
+#define GEN11_GUC_SG_INTR_MASK         _MMIO(0x1900e8)
+#define GEN11_GPM_WGBOXPERF_INTR_MASK  _MMIO(0x1900ec)
+#define GEN11_CRYPTO_RSVD_INTR_MASK    _MMIO(0x1900f0)
+#define GEN11_GUNIT_CSME_INTR_MASK     _MMIO(0x1900f4)
+
 #define ILK_DISPLAY_CHICKEN2   _MMIO(0x42004)
 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
 #define  ILK_ELPIN_409_SELECT  (1 << 25)