#include <linux/device.h>
#include <linux/string.h>
#include <linux/slab.h>
+#include <linux/amba/bus.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/hardware/amba.h>
#include <asm/sizes.h>
#define to_amba_device(d) container_of(d, struct amba_device, dev)
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/signal.h>
+#include <linux/amba/bus.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/sizes.h>
-#include <asm/hardware/amba.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
*
*/
-#include <asm/hardware/amba_clcd.h>
+#include <linux/amba/clcd.h>
struct sys_timer;
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/smp.h>
+#include <linux/amba/bus.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/io.h>
-#include <asm/hardware/amba.h>
#include <asm/hardware/arm_timer.h>
#include <asm/arch/cm.h>
#include <asm/system.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/mm.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
#include <asm/io.h>
#include <asm/hardware/icst525.h>
-#include <asm/hardware/amba.h>
-#include <asm/hardware/amba_clcd.h>
#include <asm/arch/lm.h>
#include <asm/arch/impd1.h>
#include <asm/sizes.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/kmi.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/setup.h>
#include <asm/param.h> /* HZ */
#include <asm/mach-types.h>
-#include <asm/hardware/amba.h>
-#include <asm/hardware/amba_kmi.h>
#include <asm/arch/lm.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/kmi.h>
+#include <linux/amba/clcd.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
-#include <asm/hardware/amba.h>
-#include <asm/hardware/amba_kmi.h>
-#include <asm/hardware/amba_clcd.h>
#include <asm/hardware/icst525.h>
#include <asm/arch/cm.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/device.h>
+#include <linux/amba/bus.h>
-#include <asm/hardware/amba.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <linux/dma-mapping.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/leds.h>
-#include <asm/hardware/amba.h>
-#include <asm/hardware/amba_clcd.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst307.h>
#ifndef __ASM_ARCH_REALVIEW_H
#define __ASM_ARCH_REALVIEW_H
-#include <asm/hardware/amba.h>
+#include <linux/amba/bus.h>
+
#include <asm/leds.h>
#include <asm/io.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
#include <asm/hardware/gic.h>
-#include <asm/hardware/amba.h>
#include <asm/hardware/icst307.h>
#include <asm/mach/arch.h>
#include <linux/platform_device.h>
#include <linux/sysdev.h>
#include <linux/interrupt.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/leds.h>
-#include <asm/hardware/amba.h>
-#include <asm/hardware/amba_clcd.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst307.h>
#ifndef __ASM_ARCH_VERSATILE_H
#define __ASM_ARCH_VERSATILE_H
-#include <asm/hardware/amba.h>
+#include <linux/amba/bus.h>
extern void __init versatile_init(void);
extern void __init versatile_init_irq(void);
#include <linux/init.h>
#include <linux/device.h>
#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <asm/hardware/amba.h>
#include <asm/mach/arch.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/sysdev.h>
+#include <linux/amba/bus.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
-#include <asm/hardware/amba.h>
#include <asm/mach/arch.h>
#include <asm/mach/mmc.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/err.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/kmi.h>
#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/hardware/amba.h>
-#include <asm/hardware/amba_kmi.h>
#include <asm/hardware/clock.h>
#define KMI_BASE (kmi->base)
#include <linux/highmem.h>
#include <linux/mmc/host.h>
#include <linux/mmc/protocol.h>
+#include <linux/amba/bus.h>
#include <asm/div64.h>
#include <asm/io.h>
#include <asm/scatterlist.h>
#include <asm/sizes.h>
-#include <asm/hardware/amba.h>
#include <asm/hardware/clock.h>
#include <asm/mach/mmc.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/serial.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/hardware.h>
-#include <asm/hardware/amba.h>
-#include <asm/hardware/amba_serial.h>
#define UART_NR 2
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/serial.h>
#include <asm/io.h>
#include <asm/sizes.h>
-#include <asm/hardware/amba.h>
#include <asm/hardware/clock.h>
-#include <asm/hardware/amba_serial.h>
#define UART_NR 14
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/list.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
#include <asm/sizes.h>
-#include <asm/hardware/amba.h>
#include <asm/hardware/clock.h>
-#include <asm/hardware/amba_clcd.h>
-
#define to_clcd(info) container_of(info, struct clcd_fb, fb)
/* This is limited to 16 characters when displayed by X startup */
*
*/
-#include <asm/hardware/amba_serial.h>
+#include <linux/amba/serial.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
*
*/
-#include <asm/hardware/amba_serial.h>
+#include <linux/amba/serial.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
*
*/
-#include <asm/hardware/amba_serial.h>
+#include <linux/amba/serial.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
+++ /dev/null
-/*
- * linux/include/asm-arm/hardware/amba.h
- *
- * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_AMBA_H
-#define ASMARM_AMBA_H
-
-#define AMBA_NR_IRQS 2
-
-struct amba_device {
- struct device dev;
- struct resource res;
- u64 dma_mask;
- unsigned int periphid;
- unsigned int irq[AMBA_NR_IRQS];
-};
-
-struct amba_id {
- unsigned int id;
- unsigned int mask;
- void *data;
-};
-
-struct amba_driver {
- struct device_driver drv;
- int (*probe)(struct amba_device *, void *);
- int (*remove)(struct amba_device *);
- void (*shutdown)(struct amba_device *);
- int (*suspend)(struct amba_device *, pm_message_t);
- int (*resume)(struct amba_device *);
- struct amba_id *id_table;
-};
-
-#define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
-#define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
-
-int amba_driver_register(struct amba_driver *);
-void amba_driver_unregister(struct amba_driver *);
-int amba_device_register(struct amba_device *, struct resource *);
-void amba_device_unregister(struct amba_device *);
-struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int);
-int amba_request_regions(struct amba_device *, const char *);
-void amba_release_regions(struct amba_device *);
-
-#define amba_config(d) (((d)->periphid >> 24) & 0xff)
-#define amba_rev(d) (((d)->periphid >> 20) & 0x0f)
-#define amba_manf(d) (((d)->periphid >> 12) & 0xff)
-#define amba_part(d) ((d)->periphid & 0xfff)
-
-#endif
+++ /dev/null
-/*
- * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
- *
- * David A Rusling
- *
- * Copyright (C) 2001 ARM Limited
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive
- * for more details.
- */
-#include <linux/config.h>
-#include <linux/fb.h>
-
-/*
- * CLCD Controller Internal Register addresses
- */
-#define CLCD_TIM0 0x00000000
-#define CLCD_TIM1 0x00000004
-#define CLCD_TIM2 0x00000008
-#define CLCD_TIM3 0x0000000c
-#define CLCD_UBAS 0x00000010
-#define CLCD_LBAS 0x00000014
-
-#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
-#define CLCD_IENB 0x00000018
-#define CLCD_CNTL 0x0000001c
-#else
-/*
- * Someone rearranged these two registers on the Versatile
- * platform...
- */
-#define CLCD_IENB 0x0000001c
-#define CLCD_CNTL 0x00000018
-#endif
-
-#define CLCD_STAT 0x00000020
-#define CLCD_INTR 0x00000024
-#define CLCD_UCUR 0x00000028
-#define CLCD_LCUR 0x0000002C
-#define CLCD_PALL 0x00000200
-#define CLCD_PALETTE 0x00000200
-
-#define TIM2_CLKSEL (1 << 5)
-#define TIM2_IVS (1 << 11)
-#define TIM2_IHS (1 << 12)
-#define TIM2_IPC (1 << 13)
-#define TIM2_IOE (1 << 14)
-#define TIM2_BCD (1 << 26)
-
-#define CNTL_LCDEN (1 << 0)
-#define CNTL_LCDBPP1 (0 << 1)
-#define CNTL_LCDBPP2 (1 << 1)
-#define CNTL_LCDBPP4 (2 << 1)
-#define CNTL_LCDBPP8 (3 << 1)
-#define CNTL_LCDBPP16 (4 << 1)
-#define CNTL_LCDBPP24 (5 << 1)
-#define CNTL_LCDBW (1 << 4)
-#define CNTL_LCDTFT (1 << 5)
-#define CNTL_LCDMONO8 (1 << 6)
-#define CNTL_LCDDUAL (1 << 7)
-#define CNTL_BGR (1 << 8)
-#define CNTL_BEBO (1 << 9)
-#define CNTL_BEPO (1 << 10)
-#define CNTL_LCDPWR (1 << 11)
-#define CNTL_LCDVCOMP(x) ((x) << 12)
-#define CNTL_LDMAFIFOTIME (1 << 15)
-#define CNTL_WATERMARK (1 << 16)
-
-struct clcd_panel {
- struct fb_videomode mode;
- signed short width; /* width in mm */
- signed short height; /* height in mm */
- u32 tim2;
- u32 tim3;
- u32 cntl;
- unsigned int bpp:8,
- fixedtimings:1,
- grayscale:1;
- unsigned int connector;
-};
-
-struct clcd_regs {
- u32 tim0;
- u32 tim1;
- u32 tim2;
- u32 tim3;
- u32 cntl;
- unsigned long pixclock;
-};
-
-struct clcd_fb;
-
-/*
- * the board-type specific routines
- */
-struct clcd_board {
- const char *name;
-
- /*
- * Optional. Check whether the var structure is acceptable
- * for this display.
- */
- int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
-
- /*
- * Compulsary. Decode fb->fb.var into regs->*. In the case of
- * fixed timing, set regs->* to the register values required.
- */
- void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
-
- /*
- * Optional. Disable any extra display hardware.
- */
- void (*disable)(struct clcd_fb *);
-
- /*
- * Optional. Enable any extra display hardware.
- */
- void (*enable)(struct clcd_fb *);
-
- /*
- * Setup platform specific parts of CLCD driver
- */
- int (*setup)(struct clcd_fb *);
-
- /*
- * mmap the framebuffer memory
- */
- int (*mmap)(struct clcd_fb *, struct vm_area_struct *);
-
- /*
- * Remove platform specific parts of CLCD driver
- */
- void (*remove)(struct clcd_fb *);
-};
-
-struct amba_device;
-struct clk;
-
-/* this data structure describes each frame buffer device we find */
-struct clcd_fb {
- struct fb_info fb;
- struct amba_device *dev;
- struct clk *clk;
- struct clcd_panel *panel;
- struct clcd_board *board;
- void *board_data;
- void __iomem *regs;
- u32 clcd_cntl;
- u32 cmap[16];
-};
-
-static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
-{
- u32 val, cpl;
-
- /*
- * Program the CLCD controller registers and start the CLCD
- */
- val = ((fb->fb.var.xres / 16) - 1) << 2;
- val |= (fb->fb.var.hsync_len - 1) << 8;
- val |= (fb->fb.var.right_margin - 1) << 16;
- val |= (fb->fb.var.left_margin - 1) << 24;
- regs->tim0 = val;
-
- val = fb->fb.var.yres;
- if (fb->panel->cntl & CNTL_LCDDUAL)
- val /= 2;
- val -= 1;
- val |= (fb->fb.var.vsync_len - 1) << 10;
- val |= fb->fb.var.lower_margin << 16;
- val |= fb->fb.var.upper_margin << 24;
- regs->tim1 = val;
-
- val = fb->panel->tim2;
- val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
- val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
-
- cpl = fb->fb.var.xres_virtual;
- if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */
- /* / 1 */;
- else if (!fb->fb.var.grayscale) /* STN color */
- cpl = cpl * 8 / 3;
- else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
- cpl /= 8;
- else /* STN monochrome, 4bit */
- cpl /= 4;
-
- regs->tim2 = val | ((cpl - 1) << 16);
-
- regs->tim3 = fb->panel->tim3;
-
- val = fb->panel->cntl;
- if (fb->fb.var.grayscale)
- val |= CNTL_LCDBW;
-
- switch (fb->fb.var.bits_per_pixel) {
- case 1:
- val |= CNTL_LCDBPP1;
- break;
- case 2:
- val |= CNTL_LCDBPP2;
- break;
- case 4:
- val |= CNTL_LCDBPP4;
- break;
- case 8:
- val |= CNTL_LCDBPP8;
- break;
- case 16:
- val |= CNTL_LCDBPP16;
- break;
- case 32:
- val |= CNTL_LCDBPP24;
- break;
- }
-
- regs->cntl = val;
- regs->pixclock = fb->fb.var.pixclock;
-}
-
-static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
-{
- var->xres_virtual = var->xres = (var->xres + 15) & ~15;
- var->yres_virtual = var->yres = (var->yres + 1) & ~1;
-
-#define CHECK(e,l,h) (var->e < l || var->e > h)
- if (CHECK(right_margin, (5+1), 256) || /* back porch */
- CHECK(left_margin, (5+1), 256) || /* front porch */
- CHECK(hsync_len, (5+1), 256) ||
- var->xres > 4096 ||
- var->lower_margin > 255 || /* back porch */
- var->upper_margin > 255 || /* front porch */
- var->vsync_len > 32 ||
- var->yres > 1024)
- return -EINVAL;
-#undef CHECK
-
- /* single panel mode: PCD = max(PCD, 1) */
- /* dual panel mode: PCD = max(PCD, 5) */
-
- /*
- * You can't change the grayscale setting, and
- * we can only do non-interlaced video.
- */
- if (var->grayscale != fb->fb.var.grayscale ||
- (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
- return -EINVAL;
-
-#define CHECK(e) (var->e != fb->fb.var.e)
- if (fb->panel->fixedtimings &&
- (CHECK(xres) ||
- CHECK(yres) ||
- CHECK(bits_per_pixel) ||
- CHECK(pixclock) ||
- CHECK(left_margin) ||
- CHECK(right_margin) ||
- CHECK(upper_margin) ||
- CHECK(lower_margin) ||
- CHECK(hsync_len) ||
- CHECK(vsync_len) ||
- CHECK(sync)))
- return -EINVAL;
-#undef CHECK
-
- var->nonstd = 0;
- var->accel_flags = 0;
-
- return 0;
-}
+++ /dev/null
-/*
- * linux/include/asm-arm/hardware/amba_kmi.h
- *
- * Internal header file for AMBA KMI ports
- *
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- *
- * ---------------------------------------------------------------------------
- * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
- * Reference Manual - ARM DDI 0143B - see http://www.arm.com/
- * ---------------------------------------------------------------------------
- */
-#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
-#define ASM_ARM_HARDWARE_AMBA_KMI_H
-
-/*
- * KMI control register:
- * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode
- * KMICR_RXINTREN 1 = enable RX interrupts
- * KMICR_TXINTREN 1 = enable TX interrupts
- * KMICR_EN 1 = enable KMI
- * KMICR_FD 1 = force KMI data low
- * KMICR_FC 1 = force KMI clock low
- */
-#define KMICR (KMI_BASE + 0x00)
-#define KMICR_TYPE (1 << 5)
-#define KMICR_RXINTREN (1 << 4)
-#define KMICR_TXINTREN (1 << 3)
-#define KMICR_EN (1 << 2)
-#define KMICR_FD (1 << 1)
-#define KMICR_FC (1 << 0)
-
-/*
- * KMI status register:
- * KMISTAT_TXEMPTY 1 = transmitter register empty
- * KMISTAT_TXBUSY 1 = currently sending data
- * KMISTAT_RXFULL 1 = receiver register ready to be read
- * KMISTAT_RXBUSY 1 = currently receiving data
- * KMISTAT_RXPARITY parity of last databyte received
- * KMISTAT_IC current level of KMI clock input
- * KMISTAT_ID current level of KMI data input
- */
-#define KMISTAT (KMI_BASE + 0x04)
-#define KMISTAT_TXEMPTY (1 << 6)
-#define KMISTAT_TXBUSY (1 << 5)
-#define KMISTAT_RXFULL (1 << 4)
-#define KMISTAT_RXBUSY (1 << 3)
-#define KMISTAT_RXPARITY (1 << 2)
-#define KMISTAT_IC (1 << 1)
-#define KMISTAT_ID (1 << 0)
-
-/*
- * KMI data register
- */
-#define KMIDATA (KMI_BASE + 0x08)
-
-/*
- * KMI clock divisor: to generate 8MHz internal clock
- * div = (ref / 8MHz) - 1; 0 <= div <= 15
- */
-#define KMICLKDIV (KMI_BASE + 0x0c)
-
-/*
- * KMI interrupt register:
- * KMIIR_TXINTR 1 = transmit interrupt asserted
- * KMIIR_RXINTR 1 = receive interrupt asserted
- */
-#define KMIIR (KMI_BASE + 0x10)
-#define KMIIR_TXINTR (1 << 1)
-#define KMIIR_RXINTR (1 << 0)
-
-/*
- * The size of the KMI primecell
- */
-#define KMI_SIZE (0x100)
-
-#endif
+++ /dev/null
-/*
- * linux/include/asm-arm/hardware/serial_amba.h
- *
- * Internal header file for AMBA serial ports
- *
- * Copyright (C) ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
-#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
-
-/* -------------------------------------------------------------------------------
- * From AMBA UART (PL010) Block Specification
- * -------------------------------------------------------------------------------
- * UART Register Offsets.
- */
-#define UART01x_DR 0x00 /* Data read or written from the interface. */
-#define UART01x_RSR 0x04 /* Receive status register (Read). */
-#define UART01x_ECR 0x04 /* Error clear register (Write). */
-#define UART010_LCRH 0x08 /* Line control register, high byte. */
-#define UART010_LCRM 0x0C /* Line control register, middle byte. */
-#define UART010_LCRL 0x10 /* Line control register, low byte. */
-#define UART010_CR 0x14 /* Control register. */
-#define UART01x_FR 0x18 /* Flag register (Read only). */
-#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */
-#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
-#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
-#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
-#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
-#define UART011_LCRH 0x2c /* Line control register. */
-#define UART011_CR 0x30 /* Control register. */
-#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
-#define UART011_IMSC 0x38 /* Interrupt mask. */
-#define UART011_RIS 0x3c /* Raw interrupt status. */
-#define UART011_MIS 0x40 /* Masked interrupt status. */
-#define UART011_ICR 0x44 /* Interrupt clear register. */
-#define UART011_DMACR 0x48 /* DMA control register. */
-
-#define UART011_DR_OE (1 << 11)
-#define UART011_DR_BE (1 << 10)
-#define UART011_DR_PE (1 << 9)
-#define UART011_DR_FE (1 << 8)
-
-#define UART01x_RSR_OE 0x08
-#define UART01x_RSR_BE 0x04
-#define UART01x_RSR_PE 0x02
-#define UART01x_RSR_FE 0x01
-
-#define UART011_FR_RI 0x100
-#define UART011_FR_TXFE 0x080
-#define UART011_FR_RXFF 0x040
-#define UART01x_FR_TXFF 0x020
-#define UART01x_FR_RXFE 0x010
-#define UART01x_FR_BUSY 0x008
-#define UART01x_FR_DCD 0x004
-#define UART01x_FR_DSR 0x002
-#define UART01x_FR_CTS 0x001
-#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
-
-#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
-#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
-#define UART011_CR_OUT2 0x2000 /* OUT2 */
-#define UART011_CR_OUT1 0x1000 /* OUT1 */
-#define UART011_CR_RTS 0x0800 /* RTS */
-#define UART011_CR_DTR 0x0400 /* DTR */
-#define UART011_CR_RXE 0x0200 /* receive enable */
-#define UART011_CR_TXE 0x0100 /* transmit enable */
-#define UART011_CR_LBE 0x0080 /* loopback enable */
-#define UART010_CR_RTIE 0x0040
-#define UART010_CR_TIE 0x0020
-#define UART010_CR_RIE 0x0010
-#define UART010_CR_MSIE 0x0008
-#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
-#define UART01x_CR_SIREN 0x0002 /* SIR enable */
-#define UART01x_CR_UARTEN 0x0001 /* UART enable */
-
-#define UART011_LCRH_SPS 0x80
-#define UART01x_LCRH_WLEN_8 0x60
-#define UART01x_LCRH_WLEN_7 0x40
-#define UART01x_LCRH_WLEN_6 0x20
-#define UART01x_LCRH_WLEN_5 0x00
-#define UART01x_LCRH_FEN 0x10
-#define UART01x_LCRH_STP2 0x08
-#define UART01x_LCRH_EPS 0x04
-#define UART01x_LCRH_PEN 0x02
-#define UART01x_LCRH_BRK 0x01
-
-#define UART010_IIR_RTIS 0x08
-#define UART010_IIR_TIS 0x04
-#define UART010_IIR_RIS 0x02
-#define UART010_IIR_MIS 0x01
-
-#define UART011_IFLS_RX1_8 (0 << 3)
-#define UART011_IFLS_RX2_8 (1 << 3)
-#define UART011_IFLS_RX4_8 (2 << 3)
-#define UART011_IFLS_RX6_8 (3 << 3)
-#define UART011_IFLS_RX7_8 (4 << 3)
-#define UART011_IFLS_TX1_8 (0 << 0)
-#define UART011_IFLS_TX2_8 (1 << 0)
-#define UART011_IFLS_TX4_8 (2 << 0)
-#define UART011_IFLS_TX6_8 (3 << 0)
-#define UART011_IFLS_TX7_8 (4 << 0)
-
-#define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
-#define UART011_BEIM (1 << 9) /* break error interrupt mask */
-#define UART011_PEIM (1 << 8) /* parity error interrupt mask */
-#define UART011_FEIM (1 << 7) /* framing error interrupt mask */
-#define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
-#define UART011_TXIM (1 << 5) /* transmit interrupt mask */
-#define UART011_RXIM (1 << 4) /* receive interrupt mask */
-#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
-#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
-#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
-#define UART011_RIMIM (1 << 0) /* RI interrupt mask */
-
-#define UART011_OEIS (1 << 10) /* overrun error interrupt status */
-#define UART011_BEIS (1 << 9) /* break error interrupt status */
-#define UART011_PEIS (1 << 8) /* parity error interrupt status */
-#define UART011_FEIS (1 << 7) /* framing error interrupt status */
-#define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
-#define UART011_TXIS (1 << 5) /* transmit interrupt status */
-#define UART011_RXIS (1 << 4) /* receive interrupt status */
-#define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
-#define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
-#define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
-#define UART011_RIMIS (1 << 0) /* RI interrupt status */
-
-#define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
-#define UART011_BEIC (1 << 9) /* break error interrupt clear */
-#define UART011_PEIC (1 << 8) /* parity error interrupt clear */
-#define UART011_FEIC (1 << 7) /* framing error interrupt clear */
-#define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
-#define UART011_TXIC (1 << 5) /* transmit interrupt clear */
-#define UART011_RXIC (1 << 4) /* receive interrupt clear */
-#define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
-#define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
-#define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
-#define UART011_RIMIC (1 << 0) /* RI interrupt clear */
-
-#define UART011_DMAONERR (1 << 2) /* disable dma on error */
-#define UART011_TXDMAE (1 << 1) /* enable transmit dma */
-#define UART011_RXDMAE (1 << 0) /* enable receive dma */
-
-#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
-#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
-
-#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/hardware/amba.h
+ *
+ * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_AMBA_H
+#define ASMARM_AMBA_H
+
+#define AMBA_NR_IRQS 2
+
+struct amba_device {
+ struct device dev;
+ struct resource res;
+ u64 dma_mask;
+ unsigned int periphid;
+ unsigned int irq[AMBA_NR_IRQS];
+};
+
+struct amba_id {
+ unsigned int id;
+ unsigned int mask;
+ void *data;
+};
+
+struct amba_driver {
+ struct device_driver drv;
+ int (*probe)(struct amba_device *, void *);
+ int (*remove)(struct amba_device *);
+ void (*shutdown)(struct amba_device *);
+ int (*suspend)(struct amba_device *, pm_message_t);
+ int (*resume)(struct amba_device *);
+ struct amba_id *id_table;
+};
+
+#define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
+#define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
+
+int amba_driver_register(struct amba_driver *);
+void amba_driver_unregister(struct amba_driver *);
+int amba_device_register(struct amba_device *, struct resource *);
+void amba_device_unregister(struct amba_device *);
+struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int);
+int amba_request_regions(struct amba_device *, const char *);
+void amba_release_regions(struct amba_device *);
+
+#define amba_config(d) (((d)->periphid >> 24) & 0xff)
+#define amba_rev(d) (((d)->periphid >> 20) & 0x0f)
+#define amba_manf(d) (((d)->periphid >> 12) & 0xff)
+#define amba_part(d) ((d)->periphid & 0xfff)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
+ *
+ * David A Rusling
+ *
+ * Copyright (C) 2001 ARM Limited
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+#include <linux/config.h>
+#include <linux/fb.h>
+
+/*
+ * CLCD Controller Internal Register addresses
+ */
+#define CLCD_TIM0 0x00000000
+#define CLCD_TIM1 0x00000004
+#define CLCD_TIM2 0x00000008
+#define CLCD_TIM3 0x0000000c
+#define CLCD_UBAS 0x00000010
+#define CLCD_LBAS 0x00000014
+
+#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
+#define CLCD_IENB 0x00000018
+#define CLCD_CNTL 0x0000001c
+#else
+/*
+ * Someone rearranged these two registers on the Versatile
+ * platform...
+ */
+#define CLCD_IENB 0x0000001c
+#define CLCD_CNTL 0x00000018
+#endif
+
+#define CLCD_STAT 0x00000020
+#define CLCD_INTR 0x00000024
+#define CLCD_UCUR 0x00000028
+#define CLCD_LCUR 0x0000002C
+#define CLCD_PALL 0x00000200
+#define CLCD_PALETTE 0x00000200
+
+#define TIM2_CLKSEL (1 << 5)
+#define TIM2_IVS (1 << 11)
+#define TIM2_IHS (1 << 12)
+#define TIM2_IPC (1 << 13)
+#define TIM2_IOE (1 << 14)
+#define TIM2_BCD (1 << 26)
+
+#define CNTL_LCDEN (1 << 0)
+#define CNTL_LCDBPP1 (0 << 1)
+#define CNTL_LCDBPP2 (1 << 1)
+#define CNTL_LCDBPP4 (2 << 1)
+#define CNTL_LCDBPP8 (3 << 1)
+#define CNTL_LCDBPP16 (4 << 1)
+#define CNTL_LCDBPP24 (5 << 1)
+#define CNTL_LCDBW (1 << 4)
+#define CNTL_LCDTFT (1 << 5)
+#define CNTL_LCDMONO8 (1 << 6)
+#define CNTL_LCDDUAL (1 << 7)
+#define CNTL_BGR (1 << 8)
+#define CNTL_BEBO (1 << 9)
+#define CNTL_BEPO (1 << 10)
+#define CNTL_LCDPWR (1 << 11)
+#define CNTL_LCDVCOMP(x) ((x) << 12)
+#define CNTL_LDMAFIFOTIME (1 << 15)
+#define CNTL_WATERMARK (1 << 16)
+
+struct clcd_panel {
+ struct fb_videomode mode;
+ signed short width; /* width in mm */
+ signed short height; /* height in mm */
+ u32 tim2;
+ u32 tim3;
+ u32 cntl;
+ unsigned int bpp:8,
+ fixedtimings:1,
+ grayscale:1;
+ unsigned int connector;
+};
+
+struct clcd_regs {
+ u32 tim0;
+ u32 tim1;
+ u32 tim2;
+ u32 tim3;
+ u32 cntl;
+ unsigned long pixclock;
+};
+
+struct clcd_fb;
+
+/*
+ * the board-type specific routines
+ */
+struct clcd_board {
+ const char *name;
+
+ /*
+ * Optional. Check whether the var structure is acceptable
+ * for this display.
+ */
+ int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
+
+ /*
+ * Compulsary. Decode fb->fb.var into regs->*. In the case of
+ * fixed timing, set regs->* to the register values required.
+ */
+ void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
+
+ /*
+ * Optional. Disable any extra display hardware.
+ */
+ void (*disable)(struct clcd_fb *);
+
+ /*
+ * Optional. Enable any extra display hardware.
+ */
+ void (*enable)(struct clcd_fb *);
+
+ /*
+ * Setup platform specific parts of CLCD driver
+ */
+ int (*setup)(struct clcd_fb *);
+
+ /*
+ * mmap the framebuffer memory
+ */
+ int (*mmap)(struct clcd_fb *, struct vm_area_struct *);
+
+ /*
+ * Remove platform specific parts of CLCD driver
+ */
+ void (*remove)(struct clcd_fb *);
+};
+
+struct amba_device;
+struct clk;
+
+/* this data structure describes each frame buffer device we find */
+struct clcd_fb {
+ struct fb_info fb;
+ struct amba_device *dev;
+ struct clk *clk;
+ struct clcd_panel *panel;
+ struct clcd_board *board;
+ void *board_data;
+ void __iomem *regs;
+ u32 clcd_cntl;
+ u32 cmap[16];
+};
+
+static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
+{
+ u32 val, cpl;
+
+ /*
+ * Program the CLCD controller registers and start the CLCD
+ */
+ val = ((fb->fb.var.xres / 16) - 1) << 2;
+ val |= (fb->fb.var.hsync_len - 1) << 8;
+ val |= (fb->fb.var.right_margin - 1) << 16;
+ val |= (fb->fb.var.left_margin - 1) << 24;
+ regs->tim0 = val;
+
+ val = fb->fb.var.yres;
+ if (fb->panel->cntl & CNTL_LCDDUAL)
+ val /= 2;
+ val -= 1;
+ val |= (fb->fb.var.vsync_len - 1) << 10;
+ val |= fb->fb.var.lower_margin << 16;
+ val |= fb->fb.var.upper_margin << 24;
+ regs->tim1 = val;
+
+ val = fb->panel->tim2;
+ val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
+ val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
+
+ cpl = fb->fb.var.xres_virtual;
+ if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */
+ /* / 1 */;
+ else if (!fb->fb.var.grayscale) /* STN color */
+ cpl = cpl * 8 / 3;
+ else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
+ cpl /= 8;
+ else /* STN monochrome, 4bit */
+ cpl /= 4;
+
+ regs->tim2 = val | ((cpl - 1) << 16);
+
+ regs->tim3 = fb->panel->tim3;
+
+ val = fb->panel->cntl;
+ if (fb->fb.var.grayscale)
+ val |= CNTL_LCDBW;
+
+ switch (fb->fb.var.bits_per_pixel) {
+ case 1:
+ val |= CNTL_LCDBPP1;
+ break;
+ case 2:
+ val |= CNTL_LCDBPP2;
+ break;
+ case 4:
+ val |= CNTL_LCDBPP4;
+ break;
+ case 8:
+ val |= CNTL_LCDBPP8;
+ break;
+ case 16:
+ val |= CNTL_LCDBPP16;
+ break;
+ case 32:
+ val |= CNTL_LCDBPP24;
+ break;
+ }
+
+ regs->cntl = val;
+ regs->pixclock = fb->fb.var.pixclock;
+}
+
+static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
+{
+ var->xres_virtual = var->xres = (var->xres + 15) & ~15;
+ var->yres_virtual = var->yres = (var->yres + 1) & ~1;
+
+#define CHECK(e,l,h) (var->e < l || var->e > h)
+ if (CHECK(right_margin, (5+1), 256) || /* back porch */
+ CHECK(left_margin, (5+1), 256) || /* front porch */
+ CHECK(hsync_len, (5+1), 256) ||
+ var->xres > 4096 ||
+ var->lower_margin > 255 || /* back porch */
+ var->upper_margin > 255 || /* front porch */
+ var->vsync_len > 32 ||
+ var->yres > 1024)
+ return -EINVAL;
+#undef CHECK
+
+ /* single panel mode: PCD = max(PCD, 1) */
+ /* dual panel mode: PCD = max(PCD, 5) */
+
+ /*
+ * You can't change the grayscale setting, and
+ * we can only do non-interlaced video.
+ */
+ if (var->grayscale != fb->fb.var.grayscale ||
+ (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
+ return -EINVAL;
+
+#define CHECK(e) (var->e != fb->fb.var.e)
+ if (fb->panel->fixedtimings &&
+ (CHECK(xres) ||
+ CHECK(yres) ||
+ CHECK(bits_per_pixel) ||
+ CHECK(pixclock) ||
+ CHECK(left_margin) ||
+ CHECK(right_margin) ||
+ CHECK(upper_margin) ||
+ CHECK(lower_margin) ||
+ CHECK(hsync_len) ||
+ CHECK(vsync_len) ||
+ CHECK(sync)))
+ return -EINVAL;
+#undef CHECK
+
+ var->nonstd = 0;
+ var->accel_flags = 0;
+
+ return 0;
+}
--- /dev/null
+/*
+ * linux/include/asm-arm/hardware/amba_kmi.h
+ *
+ * Internal header file for AMBA KMI ports
+ *
+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ *
+ * ---------------------------------------------------------------------------
+ * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
+ * Reference Manual - ARM DDI 0143B - see http://www.arm.com/
+ * ---------------------------------------------------------------------------
+ */
+#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
+#define ASM_ARM_HARDWARE_AMBA_KMI_H
+
+/*
+ * KMI control register:
+ * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode
+ * KMICR_RXINTREN 1 = enable RX interrupts
+ * KMICR_TXINTREN 1 = enable TX interrupts
+ * KMICR_EN 1 = enable KMI
+ * KMICR_FD 1 = force KMI data low
+ * KMICR_FC 1 = force KMI clock low
+ */
+#define KMICR (KMI_BASE + 0x00)
+#define KMICR_TYPE (1 << 5)
+#define KMICR_RXINTREN (1 << 4)
+#define KMICR_TXINTREN (1 << 3)
+#define KMICR_EN (1 << 2)
+#define KMICR_FD (1 << 1)
+#define KMICR_FC (1 << 0)
+
+/*
+ * KMI status register:
+ * KMISTAT_TXEMPTY 1 = transmitter register empty
+ * KMISTAT_TXBUSY 1 = currently sending data
+ * KMISTAT_RXFULL 1 = receiver register ready to be read
+ * KMISTAT_RXBUSY 1 = currently receiving data
+ * KMISTAT_RXPARITY parity of last databyte received
+ * KMISTAT_IC current level of KMI clock input
+ * KMISTAT_ID current level of KMI data input
+ */
+#define KMISTAT (KMI_BASE + 0x04)
+#define KMISTAT_TXEMPTY (1 << 6)
+#define KMISTAT_TXBUSY (1 << 5)
+#define KMISTAT_RXFULL (1 << 4)
+#define KMISTAT_RXBUSY (1 << 3)
+#define KMISTAT_RXPARITY (1 << 2)
+#define KMISTAT_IC (1 << 1)
+#define KMISTAT_ID (1 << 0)
+
+/*
+ * KMI data register
+ */
+#define KMIDATA (KMI_BASE + 0x08)
+
+/*
+ * KMI clock divisor: to generate 8MHz internal clock
+ * div = (ref / 8MHz) - 1; 0 <= div <= 15
+ */
+#define KMICLKDIV (KMI_BASE + 0x0c)
+
+/*
+ * KMI interrupt register:
+ * KMIIR_TXINTR 1 = transmit interrupt asserted
+ * KMIIR_RXINTR 1 = receive interrupt asserted
+ */
+#define KMIIR (KMI_BASE + 0x10)
+#define KMIIR_TXINTR (1 << 1)
+#define KMIIR_RXINTR (1 << 0)
+
+/*
+ * The size of the KMI primecell
+ */
+#define KMI_SIZE (0x100)
+
+#endif
--- /dev/null
+/*
+ * linux/include/asm-arm/hardware/serial_amba.h
+ *
+ * Internal header file for AMBA serial ports
+ *
+ * Copyright (C) ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
+#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
+
+/* -------------------------------------------------------------------------------
+ * From AMBA UART (PL010) Block Specification
+ * -------------------------------------------------------------------------------
+ * UART Register Offsets.
+ */
+#define UART01x_DR 0x00 /* Data read or written from the interface. */
+#define UART01x_RSR 0x04 /* Receive status register (Read). */
+#define UART01x_ECR 0x04 /* Error clear register (Write). */
+#define UART010_LCRH 0x08 /* Line control register, high byte. */
+#define UART010_LCRM 0x0C /* Line control register, middle byte. */
+#define UART010_LCRL 0x10 /* Line control register, low byte. */
+#define UART010_CR 0x14 /* Control register. */
+#define UART01x_FR 0x18 /* Flag register (Read only). */
+#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */
+#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
+#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
+#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
+#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
+#define UART011_LCRH 0x2c /* Line control register. */
+#define UART011_CR 0x30 /* Control register. */
+#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
+#define UART011_IMSC 0x38 /* Interrupt mask. */
+#define UART011_RIS 0x3c /* Raw interrupt status. */
+#define UART011_MIS 0x40 /* Masked interrupt status. */
+#define UART011_ICR 0x44 /* Interrupt clear register. */
+#define UART011_DMACR 0x48 /* DMA control register. */
+
+#define UART011_DR_OE (1 << 11)
+#define UART011_DR_BE (1 << 10)
+#define UART011_DR_PE (1 << 9)
+#define UART011_DR_FE (1 << 8)
+
+#define UART01x_RSR_OE 0x08
+#define UART01x_RSR_BE 0x04
+#define UART01x_RSR_PE 0x02
+#define UART01x_RSR_FE 0x01
+
+#define UART011_FR_RI 0x100
+#define UART011_FR_TXFE 0x080
+#define UART011_FR_RXFF 0x040
+#define UART01x_FR_TXFF 0x020
+#define UART01x_FR_RXFE 0x010
+#define UART01x_FR_BUSY 0x008
+#define UART01x_FR_DCD 0x004
+#define UART01x_FR_DSR 0x002
+#define UART01x_FR_CTS 0x001
+#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
+
+#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
+#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
+#define UART011_CR_OUT2 0x2000 /* OUT2 */
+#define UART011_CR_OUT1 0x1000 /* OUT1 */
+#define UART011_CR_RTS 0x0800 /* RTS */
+#define UART011_CR_DTR 0x0400 /* DTR */
+#define UART011_CR_RXE 0x0200 /* receive enable */
+#define UART011_CR_TXE 0x0100 /* transmit enable */
+#define UART011_CR_LBE 0x0080 /* loopback enable */
+#define UART010_CR_RTIE 0x0040
+#define UART010_CR_TIE 0x0020
+#define UART010_CR_RIE 0x0010
+#define UART010_CR_MSIE 0x0008
+#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
+#define UART01x_CR_SIREN 0x0002 /* SIR enable */
+#define UART01x_CR_UARTEN 0x0001 /* UART enable */
+
+#define UART011_LCRH_SPS 0x80
+#define UART01x_LCRH_WLEN_8 0x60
+#define UART01x_LCRH_WLEN_7 0x40
+#define UART01x_LCRH_WLEN_6 0x20
+#define UART01x_LCRH_WLEN_5 0x00
+#define UART01x_LCRH_FEN 0x10
+#define UART01x_LCRH_STP2 0x08
+#define UART01x_LCRH_EPS 0x04
+#define UART01x_LCRH_PEN 0x02
+#define UART01x_LCRH_BRK 0x01
+
+#define UART010_IIR_RTIS 0x08
+#define UART010_IIR_TIS 0x04
+#define UART010_IIR_RIS 0x02
+#define UART010_IIR_MIS 0x01
+
+#define UART011_IFLS_RX1_8 (0 << 3)
+#define UART011_IFLS_RX2_8 (1 << 3)
+#define UART011_IFLS_RX4_8 (2 << 3)
+#define UART011_IFLS_RX6_8 (3 << 3)
+#define UART011_IFLS_RX7_8 (4 << 3)
+#define UART011_IFLS_TX1_8 (0 << 0)
+#define UART011_IFLS_TX2_8 (1 << 0)
+#define UART011_IFLS_TX4_8 (2 << 0)
+#define UART011_IFLS_TX6_8 (3 << 0)
+#define UART011_IFLS_TX7_8 (4 << 0)
+
+#define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
+#define UART011_BEIM (1 << 9) /* break error interrupt mask */
+#define UART011_PEIM (1 << 8) /* parity error interrupt mask */
+#define UART011_FEIM (1 << 7) /* framing error interrupt mask */
+#define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
+#define UART011_TXIM (1 << 5) /* transmit interrupt mask */
+#define UART011_RXIM (1 << 4) /* receive interrupt mask */
+#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
+#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
+#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
+#define UART011_RIMIM (1 << 0) /* RI interrupt mask */
+
+#define UART011_OEIS (1 << 10) /* overrun error interrupt status */
+#define UART011_BEIS (1 << 9) /* break error interrupt status */
+#define UART011_PEIS (1 << 8) /* parity error interrupt status */
+#define UART011_FEIS (1 << 7) /* framing error interrupt status */
+#define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
+#define UART011_TXIS (1 << 5) /* transmit interrupt status */
+#define UART011_RXIS (1 << 4) /* receive interrupt status */
+#define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
+#define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
+#define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
+#define UART011_RIMIS (1 << 0) /* RI interrupt status */
+
+#define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
+#define UART011_BEIC (1 << 9) /* break error interrupt clear */
+#define UART011_PEIC (1 << 8) /* parity error interrupt clear */
+#define UART011_FEIC (1 << 7) /* framing error interrupt clear */
+#define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
+#define UART011_TXIC (1 << 5) /* transmit interrupt clear */
+#define UART011_RXIC (1 << 4) /* receive interrupt clear */
+#define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
+#define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
+#define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
+#define UART011_RIMIC (1 << 0) /* RI interrupt clear */
+
+#define UART011_DMAONERR (1 << 2) /* disable dma on error */
+#define UART011_TXDMAE (1 << 1) /* enable transmit dma */
+#define UART011_RXDMAE (1 << 0) /* enable receive dma */
+
+#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
+#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
+
+#endif
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/err.h>
+#include <linux/amba/bus.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/sizes.h>
-#include <asm/hardware/amba.h>
#include <sound/driver.h>
#include <sound/core.h>
projects / openwrt / staging / blogic.git / commitdiff