ARM: dts: r7s9210: Add SDHI support

Add SDHI support for the R7S9210 (RZ/A2) SoC.

Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 1cd982c9920f8565964e6a64c4b8d592fb3e8679..2eaa5eeba509478f030477b5e7439aa19f406c04 100644 (file)
--- a/arch/arm/boot/dts/r7s9210.dtsi
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -322,6 +322,30 @@
                        status = "disabled";
                };
 
+               sdhi0: sd@e8228000 {
+                       compatible = "renesas,sdhi-r7s9210";
+                       reg = <0xe8228000 0x8c0>;
+                       interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 102>;
+                       clock-names = "core", "cd";
+                       power-domains = <&cpg>;
+                       cap-sd-highspeed;
+                       cap-sdio-irq;
+                       status = "disabled";
+               };
+
+               sdhi1: sd@e822a000 {
+                       compatible = "renesas,sdhi-r7s9210";
+                       reg = <0xe822a000 0x8c0>;
+                       interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 101>, <&cpg CPG_MOD 100>;
+                       clock-names = "core", "cd";
+                       power-domains = <&cpg>;
+                       cap-sd-highspeed;
+                       cap-sdio-irq;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@e8221000 {
                        compatible = "arm,gic-400";
                        #interrupt-cells = <3>;