drm/amdgpu/VCN2.5: set encode ring functions

Also reuse most of the VCN2.0 encode ring functions

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index f16a4f682e260f6eeb4a68598995a83aefee140a..b42f6769ae0611945af8239adb76090a3f010e4f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -819,12 +819,103 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 };
 
+/**
+ * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc read pointer
+ */
+static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
+{
+       struct amdgpu_device *adev = ring->adev;
+
+       if (ring == &adev->vcn.ring_enc[0])
+               return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
+       else
+               return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
+}
+
+/**
+ * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Returns the current hardware enc write pointer
+ */
+static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
+{
+       struct amdgpu_device *adev = ring->adev;
+
+       if (ring == &adev->vcn.ring_enc[0])
+               return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
+       else
+               return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
+}
+
+/**
+ * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
+ *
+ * @ring: amdgpu_ring pointer
+ *
+ * Commits the enc write pointer to the hardware
+ */
+static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
+{
+       struct amdgpu_device *adev = ring->adev;
+
+       if (ring == &adev->vcn.ring_enc[0])
+               WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+       else
+               WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+}
+
+static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
+       .type = AMDGPU_RING_TYPE_VCN_ENC,
+       .align_mask = 0x3f,
+       .nop = VCN_ENC_CMD_NO_OP,
+       .vmhub = AMDGPU_MMHUB_1,
+       .get_rptr = vcn_v2_5_enc_ring_get_rptr,
+       .get_wptr = vcn_v2_5_enc_ring_get_wptr,
+       .set_wptr = vcn_v2_5_enc_ring_set_wptr,
+       .emit_frame_size =
+               SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
+               SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
+               4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
+               5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
+               1, /* vcn_v2_0_enc_ring_insert_end */
+       .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
+       .emit_ib = vcn_v2_0_enc_ring_emit_ib,
+       .emit_fence = vcn_v2_0_enc_ring_emit_fence,
+       .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
+       .test_ring = amdgpu_vcn_enc_ring_test_ring,
+       .test_ib = amdgpu_vcn_enc_ring_test_ib,
+       .insert_nop = amdgpu_ring_insert_nop,
+       .insert_end = vcn_v2_0_enc_ring_insert_end,
+       .pad_ib = amdgpu_ring_generic_pad_ib,
+       .begin_use = amdgpu_vcn_ring_begin_use,
+       .end_use = amdgpu_vcn_ring_end_use,
+       .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
+       .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
+       .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+};
+
 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
 {
        adev->vcn.ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
        DRM_INFO("VCN decode is enabled in VM mode\n");
 }
 
+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+{
+       int i;
+
+       for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+               adev->vcn.ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
+
+       DRM_INFO("VCN encode is enabled in VM mode\n");
+}
+
 static bool vcn_v2_5_is_idle(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;