drm/amd/display: add calculated clock logging to DTN

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7dd130d15a671178f285b83db49479c301f94e0e..e547f46d3516230302b744d2d9d05785bc8bc838 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -311,7 +311,16 @@ void dcn10_log_hw_state(struct dc *dc)
                print_rq_dlg_ttu_regs(dc_ctx, &s);
                DTN_INFO("\n");
        }
-       DTN_INFO("\n");
+
+       DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
+               "dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
+                       dc->current_state->bw.dcn.calc_clk.dcfclk_khz,
+                       dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
+                       dc->current_state->bw.dcn.calc_clk.dispclk_khz,
+                       dc->current_state->bw.dcn.calc_clk.dppclk_khz,
+                       dc->current_state->bw.dcn.calc_clk.max_supported_dppclk_khz,
+                       dc->current_state->bw.dcn.calc_clk.fclk_khz,
+                       dc->current_state->bw.dcn.calc_clk.socclk_khz);
 
        log_mpc_crc(dc);