#include <platform_def.h>
#include <cortex_a75.h>
- .globl plat_is_my_cpu_primary
.globl plat_arm_calc_core_pos
.globl plat_reset_handler
- /* -----------------------------------------------------
- * unsigned int plat_is_my_cpu_primary (void);
- *
- * Find out whether the current cpu is the primary
- * cpu (applicable only after a cold boot)
- * -----------------------------------------------------
- */
-func plat_is_my_cpu_primary
- mov x9, x30
- bl plat_my_core_pos
- ldr x1, =SGI_BOOT_CFG_ADDR
- ldr x1, [x1]
- ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
- #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
- cmp x0, x1
- cset w0, eq
- ret x9
-endfunc plat_is_my_cpu_primary
-
/* -----------------------------------------------------
* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
*
CSS_SGI_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
-#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000
-#define SGI_BOOT_CFG_ADDR 0x45410000
-#define PLAT_CSS_PRIMARY_CPU_SHIFT 8
-#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 6
-
/* GIC related constants */
#define PLAT_ARM_GICD_BASE 0x30000000
#define PLAT_ARM_GICC_BASE 0x2C000000
# SPDX-License-Identifier: BSD-3-Clause
#
+CSS_USE_SCMI_SDS_DRIVER := 1
+
ENABLE_PLAT_COMPAT := 0
CSS_ENT_BASE := plat/arm/css/sgi
{
return sgi_topology.plat_cluster_core_count;
}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+};