arm64: dts: sc7180: add display dt nodes

Add display, DSI hardware DT nodes for sc7180.

Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Co-developed-by: Kalyan Thota <kalyan_t@codeaurora.org>
Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org>
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Link: https://lore.kernel.org/r/1580825707-27115-1-git-send-email-harigovi@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 7cebc1fad7e079e84b4aca8478ae4fc9a99fa263..253274d5f04cb335930575c45d138220aab3e694 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1386,13 +1386,145 @@
                        #power-domain-cells = <1>;
                };
 
+               mdss: mdss@ae00000 {
+                       compatible = "qcom,sc7180-mdss";
+                       reg = <0 0x0ae00000 0 0x1000>;
+                       reg-names = "mdss";
+
+                       power-domains = <&dispcc MDSS_GDSC>;
+
+                       clocks = <&gcc GCC_DISP_AHB_CLK>,
+                                <&gcc GCC_DISP_HF_AXI_CLK>,
+                                <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                <&dispcc DISP_CC_MDSS_MDP_CLK>;
+                       clock-names = "iface", "bus", "ahb", "core";
+
+                       assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
+                       assigned-clock-rates = <300000000>;
+
+                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       iommus = <&apps_smmu 0x800 0x2>;
+
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       status = "disabled";
+
+                       mdp: mdp@ae01000 {
+                               compatible = "qcom,sc7180-dpu";
+                               reg = <0 0x0ae01000 0 0x8f000>,
+                                     <0 0x0aeb0000 0 0x2008>;
+                               reg-names = "mdp", "vbif";
+
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&dispcc DISP_CC_MDSS_ROT_CLK>,
+                                        <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+                                        <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                                        <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+                               clock-names = "iface", "rot", "lut", "core",
+                                             "vsync";
+                               assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                                                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+                               assigned-clock-rates = <300000000>,
+                                                      <19200000>;
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               dpu_intf1_out: endpoint {
+                                                       remote-endpoint = <&dsi0_in>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       dsi0: dsi@ae94000 {
+                               compatible = "qcom,mdss-dsi-ctrl";
+                               reg = <0 0x0ae94000 0 0x400>;
+                               reg-names = "dsi_ctrl";
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+                               clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                                        <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&gcc GCC_DISP_HF_AXI_CLK>;
+                               clock-names = "byte",
+                                             "byte_intf",
+                                             "pixel",
+                                             "core",
+                                             "iface",
+                                             "bus";
+
+                               phys = <&dsi_phy>;
+                               phy-names = "dsi";
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               dsi0_in: endpoint {
+                                                       remote-endpoint = <&dpu_intf1_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                               dsi0_out: endpoint {
+                                               };
+                                       };
+                               };
+                       };
+
+                       dsi_phy: dsi-phy@ae94400 {
+                               compatible = "qcom,dsi-phy-10nm";
+                               reg = <0 0x0ae94400 0 0x200>,
+                                     <0 0x0ae94600 0 0x280>,
+                                     <0 0x0ae94a00 0 0x1e0>;
+                               reg-names = "dsi_phy",
+                                           "dsi_phy_lane",
+                                           "dsi_pll";
+
+                               #clock-cells = <1>;
+                               #phy-cells = <0>;
+
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&rpmhcc RPMH_CXO_CLK>;
+                               clock-names = "iface", "ref";
+
+                               status = "disabled";
+                       };
+               };
+
                dispcc: clock-controller@af00000 {
                        compatible = "qcom,sc7180-dispcc";
                        reg = <0 0x0af00000 0 0x200000>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
-                                <0>,
-                                <0>,
+                                <&dsi_phy 0>,
+                                <&dsi_phy 1>,
                                 <0>,
                                 <0>;
                        clock-names = "bi_tcxo",