Fixes build failure when having kmod-mmc and brcmfmac selected.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 36468
--- /dev/null
+/*
+ * Copyright (c) 2013 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _LINUX_BRCMFMAC_PLATFORM_H
+#define _LINUX_BRCMFMAC_PLATFORM_H
+
+/*
+ * Platform specific driver functions and data. Through the platform specific
+ * device data functions can be provided to help the brcmfmac driver to
+ * operate with the device in combination with the used platform.
+ *
+ * Use the platform data in the following (similar) way:
+ *
+ *
+#include <brcmfmac_platform.h>
+
+
+static void brcmfmac_power_on(void)
+{
+}
+
+static void brcmfmac_power_off(void)
+{
+}
+
+static void brcmfmac_reset(void)
+{
+}
+
+static struct brcmfmac_sdio_platform_data brcmfmac_sdio_pdata = {
+ .power_on = brcmfmac_power_on,
+ .power_off = brcmfmac_power_off,
+ .reset = brcmfmac_reset
+};
+
+static struct platform_device brcmfmac_device = {
+ .name = BRCMFMAC_SDIO_PDATA_NAME,
+ .id = PLATFORM_DEVID_NONE,
+ .dev.platform_data = &brcmfmac_sdio_pdata
+};
+
+void __init brcmfmac_init_pdata(void)
+{
+ brcmfmac_sdio_pdata.oob_irq_supported = true;
+ brcmfmac_sdio_pdata.oob_irq_nr = gpio_to_irq(GPIO_BRCMF_SDIO_OOB);
+ brcmfmac_sdio_pdata.oob_irq_flags = IORESOURCE_IRQ |
+ IORESOURCE_IRQ_HIGHLEVEL;
+ platform_device_register(&brcmfmac_device);
+}
+ *
+ *
+ * Note: the brcmfmac can be loaded as module or be statically built-in into
+ * the kernel. If built-in then do note that it uses module_init (and
+ * module_exit) routines which equal device_initcall. So if you intend to
+ * create a module with the platform specific data for the brcmfmac and have
+ * it built-in to the kernel then use a higher initcall then device_initcall
+ * (see init.h). If this is not done then brcmfmac will load without problems
+ * but will not pickup the platform data.
+ *
+ * When the driver does not "detect" platform driver data then it will continue
+ * without reporting anything and just assume there is no data needed. Which is
+ * probably true for most platforms.
+ *
+ * Explanation of the platform_data fields:
+ *
+ * drive_strength: is the preferred drive_strength to be used for the SDIO
+ * pins. If 0 then a default value will be used. This is the target drive
+ * strength, the exact drive strength which will be used depends on the
+ * capabilities of the device.
+ *
+ * oob_irq_supported: does the board have support for OOB interrupts. SDIO
+ * in-band interrupts are relatively slow and for having less overhead on
+ * interrupt processing an out of band interrupt can be used. If the HW
+ * supports this then enable this by setting this field to true and configure
+ * the oob related fields.
+ *
+ * oob_irq_nr, oob_irq_flags: the OOB interrupt information. The values are
+ * used for registering the irq using request_irq function.
+ *
+ * power_on: This function is called by the brcmfmac when the module gets
+ * loaded. This can be particularly useful for low power devices. The platform
+ * spcific routine may for example decide to power up the complete device.
+ * If there is no use-case for this function then provide NULL.
+ *
+ * power_off: This function is called by the brcmfmac when the module gets
+ * unloaded. At this point the device can be powered down or otherwise be reset.
+ * So if an actual power_off is not supported but reset is then reset the device
+ * when this function gets called. This can be particularly useful for low power
+ * devices. If there is no use-case for this function (either power-down or
+ * reset) then provide NULL.
+ *
+ * reset: This function can get called if the device communication broke down.
+ * This functionality is particularly useful in case of SDIO type devices. It is
+ * possible to reset a dongle via sdio data interface, but it requires that
+ * this is fully functional. This function is chip/module specific and this
+ * function should return only after the complete reset has completed.
+ */
+
+#define BRCMFMAC_SDIO_PDATA_NAME "brcmfmac_sdio"
+
+struct brcmfmac_sdio_platform_data {
+ unsigned int drive_strength;
+ bool oob_irq_supported;
+ unsigned int oob_irq_nr;
+ unsigned long oob_irq_flags;
+ void (*power_on)(void);
+ void (*power_off)(void);
+ void (*reset)(void);
+};
+
+#endif /* _LINUX_BRCMFMAC_PLATFORM_H */
+}
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
-@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
+@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
{
struct ssb_bus *bus = mcore->dev->bus;
bcma_core_mips_print_irq(core, bcma_core_mips_irq(core));
}
}
-@@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+@@ -171,9 +194,9 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
struct bcma_bus *bus = mcore->core->bus;
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
}
/**************************************************
-@@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
+@@ -138,88 +143,108 @@ static void bcma_pcie_mdio_write(struct
static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc)
{
{
struct bcma_bus *bus = pci_get_drvdata(dev);
-@@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct
+@@ -234,7 +238,7 @@ static void bcma_host_pci_remove(struct
pci_set_drvdata(dev, NULL);
}
+ break;
+ default:
+ return "UNKNOWN";
-+ }
+ }
+
+ for (i = 0; i < size; i++) {
+ if (names[i].id == id->id)
+ return names[i].name;
- }
++ }
+
return "UNKNOWN";
}
+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
+ }
-+
+
+- bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
+- SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
+- bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
+- SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
+- bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
+- SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
+- bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
+- SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
+-
+- bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
+- SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
+- bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
+- SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
+- bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
+- SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
+- bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
+- SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
+-
+- bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
+- SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
+- bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
+- SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
+- bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
+- SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
+- bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
+- SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
+-
+- bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
+- SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
+- bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
+- SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
+- bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
+- SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
+- bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
+- SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
+-
+- bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
+- bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
+- bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
+- bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
+-
+- bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
+-
+- bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
+- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
+- bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
+- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
+- bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
+- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
+- bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
+- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
+- bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
+- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
+-
+- bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
+- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
+- bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
+- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
+- bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
+- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
+- bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
+- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
+- bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
+- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
+ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_TSSIPOS,
+ SSB_SROM8_FEM_TSSIPOS_SHIFT);
+ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G, SSB_SROM8_FEM_EXTPA_GAIN,
+ case BCMA_CHIP_ID_BCM4331:
+ present_mask = BCMA_CC_CHIPST_4331_SPROM_PRESENT;
+ break;
-
-- bus->sprom.txpid2g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
-- SSB_SPROM4_TXPID2G0) >> SSB_SPROM4_TXPID2G0_SHIFT;
-- bus->sprom.txpid2g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID2G01)] &
-- SSB_SPROM4_TXPID2G1) >> SSB_SPROM4_TXPID2G1_SHIFT;
-- bus->sprom.txpid2g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
-- SSB_SPROM4_TXPID2G2) >> SSB_SPROM4_TXPID2G2_SHIFT;
-- bus->sprom.txpid2g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID2G23)] &
-- SSB_SPROM4_TXPID2G3) >> SSB_SPROM4_TXPID2G3_SHIFT;
--
-- bus->sprom.txpid5gl[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
-- SSB_SPROM4_TXPID5GL0) >> SSB_SPROM4_TXPID5GL0_SHIFT;
-- bus->sprom.txpid5gl[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL01)] &
-- SSB_SPROM4_TXPID5GL1) >> SSB_SPROM4_TXPID5GL1_SHIFT;
-- bus->sprom.txpid5gl[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
-- SSB_SPROM4_TXPID5GL2) >> SSB_SPROM4_TXPID5GL2_SHIFT;
-- bus->sprom.txpid5gl[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GL23)] &
-- SSB_SPROM4_TXPID5GL3) >> SSB_SPROM4_TXPID5GL3_SHIFT;
--
-- bus->sprom.txpid5g[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
-- SSB_SPROM4_TXPID5G0) >> SSB_SPROM4_TXPID5G0_SHIFT;
-- bus->sprom.txpid5g[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5G01)] &
-- SSB_SPROM4_TXPID5G1) >> SSB_SPROM4_TXPID5G1_SHIFT;
-- bus->sprom.txpid5g[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
-- SSB_SPROM4_TXPID5G2) >> SSB_SPROM4_TXPID5G2_SHIFT;
-- bus->sprom.txpid5g[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5G23)] &
-- SSB_SPROM4_TXPID5G3) >> SSB_SPROM4_TXPID5G3_SHIFT;
--
-- bus->sprom.txpid5gh[0] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
-- SSB_SPROM4_TXPID5GH0) >> SSB_SPROM4_TXPID5GH0_SHIFT;
-- bus->sprom.txpid5gh[1] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH01)] &
-- SSB_SPROM4_TXPID5GH1) >> SSB_SPROM4_TXPID5GH1_SHIFT;
-- bus->sprom.txpid5gh[2] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
-- SSB_SPROM4_TXPID5GH2) >> SSB_SPROM4_TXPID5GH2_SHIFT;
-- bus->sprom.txpid5gh[3] = (sprom[SPOFF(SSB_SPROM4_TXPID5GH23)] &
-- SSB_SPROM4_TXPID5GH3) >> SSB_SPROM4_TXPID5GH3_SHIFT;
--
-- bus->sprom.boardflags_lo = sprom[SPOFF(SSB_SPROM8_BFLLO)];
-- bus->sprom.boardflags_hi = sprom[SPOFF(SSB_SPROM8_BFLHI)];
-- bus->sprom.boardflags2_lo = sprom[SPOFF(SSB_SPROM8_BFL2LO)];
-- bus->sprom.boardflags2_hi = sprom[SPOFF(SSB_SPROM8_BFL2HI)];
--
-- bus->sprom.country_code = sprom[SPOFF(SSB_SPROM8_CCODE)];
--
-- bus->sprom.fem.ghz2.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
-- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
-- bus->sprom.fem.ghz2.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
-- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
-- bus->sprom.fem.ghz2.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
-- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
-- bus->sprom.fem.ghz2.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
-- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
-- bus->sprom.fem.ghz2.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM2G)] &
-- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
--
-- bus->sprom.fem.ghz5.tssipos = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
-- SSB_SROM8_FEM_TSSIPOS) >> SSB_SROM8_FEM_TSSIPOS_SHIFT;
-- bus->sprom.fem.ghz5.extpa_gain = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
-- SSB_SROM8_FEM_EXTPA_GAIN) >> SSB_SROM8_FEM_EXTPA_GAIN_SHIFT;
-- bus->sprom.fem.ghz5.pdet_range = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
-- SSB_SROM8_FEM_PDET_RANGE) >> SSB_SROM8_FEM_PDET_RANGE_SHIFT;
-- bus->sprom.fem.ghz5.tr_iso = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
-- SSB_SROM8_FEM_TR_ISO) >> SSB_SROM8_FEM_TR_ISO_SHIFT;
-- bus->sprom.fem.ghz5.antswlut = (sprom[SPOFF(SSB_SPROM8_FEM5G)] &
-- SSB_SROM8_FEM_ANTSWLUT) >> SSB_SROM8_FEM_ANTSWLUT_SHIFT;
++
+ default:
+ return true;
+ }
#define BCMA_CORE_INVALID 0x700
#define BCMA_CORE_CHIPCOMMON 0x800
#define BCMA_CORE_ILINE20 0x801
-@@ -125,6 +138,41 @@ struct bcma_host_ops {
+@@ -121,10 +134,46 @@ struct bcma_host_ops {
+ #define BCMA_CORE_I2S 0x834
+ #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
+ #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
++#define BCMA_CORE_ARM_CR4 0x83e
+ #define BCMA_CORE_DEFAULT 0xFFF
#define BCMA_MAX_NR_CORES 16
struct bcma_device {
struct bcma_bus *bus;
struct bcma_device_id id;
-@@ -136,8 +184,10 @@ struct bcma_device {
+@@ -136,8 +185,10 @@ struct bcma_device {
bool dev_registered;
u8 core_index;
u32 wrap;
void __iomem *io_addr;
-@@ -175,6 +225,12 @@ int __bcma_driver_register(struct bcma_d
+@@ -175,6 +226,12 @@ int __bcma_driver_register(struct bcma_d
extern void bcma_driver_unregister(struct bcma_driver *drv);
struct bcma_bus {
/* The MMIO area. */
void __iomem *mmio;
-@@ -191,14 +247,18 @@ struct bcma_bus {
+@@ -191,14 +248,18 @@ struct bcma_bus {
struct bcma_chipinfo chipinfo;
/* We decided to share SPROM struct with SSB as long as we do not need
* any hacks for BCMA. This simplifies drivers code. */
-@@ -282,6 +342,7 @@ static inline void bcma_maskset16(struct
+@@ -282,6 +343,7 @@ static inline void bcma_maskset16(struct
bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
}
extern bool bcma_core_is_enabled(struct bcma_device *core);
extern void bcma_core_disable(struct bcma_device *core, u32 flags);
extern int bcma_core_enable(struct bcma_device *core, u32 flags);
-@@ -289,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
+@@ -289,6 +351,7 @@ extern void bcma_core_set_clockmode(stru
enum bcma_clkmode clkmode);
extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
bool on);
/* 0x1E0 is defined as shared BCMA_CLKCTLST */
#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
#define BCMA_CC_UART0_DATA 0x0300
-@@ -240,7 +353,60 @@
+@@ -203,6 +316,9 @@
+ #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
+ #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
+ #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
++#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
++#define BCMA_CC_PMU_CTL_RES_SHIFT 13
++#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
+ #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
+ #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
+ #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
+@@ -240,7 +356,60 @@
#define BCMA_CC_PLLCTL_ADDR 0x0660
#define BCMA_CC_PLLCTL_DATA 0x0664
#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
/* Divider allocation in 4716/47162/5356 */
#define BCMA_CC_PMU5_MAINPLL_CPU 1
-@@ -256,6 +422,15 @@
+@@ -256,6 +425,15 @@
/* 4706 PMU */
#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
/* ALP clock on pre-PMU chips */
#define BCMA_CC_PMU_ALP_CLOCK 20000000
-@@ -284,6 +459,19 @@
+@@ -284,6 +462,19 @@
#define BCMA_CC_PPL_PCHI_OFF 5
#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
/* BCM4331 ChipControl numbers. */
#define BCMA_CHIPCTL_4331_BT_COEXIST BIT(0) /* 0 disable */
#define BCMA_CHIPCTL_4331_SECI BIT(1) /* 0 SECI is disabled (JATG functional) */
-@@ -297,9 +485,25 @@
+@@ -297,9 +488,25 @@
#define BCMA_CHIPCTL_4331_OVR_PIPEAUXPWRDOWN BIT(9) /* override core control on pipe_AuxPowerDown */
#define BCMA_CHIPCTL_4331_PCIE_AUXCLKEN BIT(10) /* pcie_auxclkenable */
#define BCMA_CHIPCTL_4331_PCIE_PIPE_PLLDOWN BIT(11) /* pcie_pipe_pllpowerdown */
/* Data for the PMU, if available.
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
*/
-@@ -310,11 +514,35 @@ struct bcma_chipcommon_pmu {
+@@ -310,11 +517,35 @@ struct bcma_chipcommon_pmu {
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash {
struct bcma_serial_port {
void *regs;
unsigned long clockspeed;
-@@ -330,15 +558,30 @@ struct bcma_drv_cc {
+@@ -330,15 +561,30 @@ struct bcma_drv_cc {
u32 capabilities;
u32 capabilities_ext;
u8 setup_done:1;
};
/* Register access */
-@@ -355,14 +598,16 @@ struct bcma_drv_cc {
+@@ -355,14 +601,16 @@ struct bcma_drv_cc {
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
-@@ -375,9 +620,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
+@@ -375,9 +623,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
u32 value);
-@@ -387,5 +635,6 @@ extern void bcma_chipco_chipctl_maskset(
+@@ -387,5 +638,6 @@ extern void bcma_chipco_chipctl_maskset(
u32 offset, u32 mask, u32 set);
extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
u32 offset, u32 mask, u32 set);
/* Is there any BCM4328 on BCMA bus? */
#define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
#define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
-@@ -56,4 +58,36 @@
+@@ -35,6 +37,7 @@
+ #define BCMA_IOST_BIST_DONE 0x8000
+ #define BCMA_RESET_CTL 0x0800
+ #define BCMA_RESET_CTL_RESET 0x0001
++#define BCMA_RESET_ST 0x0804
+
+ /* BCMA PCI config space registers. */
+ #define BCMA_PCI_PMCSR 0x44
+@@ -56,4 +59,36 @@
#define BCMA_PCI_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
#define BCMA_PCI_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
--- a/net/netfilter/nf_conntrack_standalone.c
+++ b/net/netfilter/nf_conntrack_standalone.c
-@@ -267,10 +267,34 @@ static int ct_open(struct inode *inode,
+@@ -267,10 +267,34 @@ static int ct_open(struct inode *inode,
sizeof(struct ct_iter_state));
}
+}
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
-@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
+@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
{
struct ssb_bus *bus = mcore->dev->bus;
for (i = 0; i <= 6; i++)
printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
printk("\n");
-@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
struct bcma_bus *bus = mcore->core->bus;
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
}
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
return ret;
-@@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
+@@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
break;
struct bcma_device;
struct bcma_bus;
-@@ -157,6 +157,7 @@ struct bcma_host_ops {
+@@ -134,6 +134,7 @@ struct bcma_host_ops {
+ #define BCMA_CORE_I2S 0x834
+ #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
+ #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
++#define BCMA_CORE_ARM_CR4 0x83e
+ #define BCMA_CORE_DEFAULT 0xFFF
+
+ #define BCMA_MAX_NR_CORES 16
+@@ -157,6 +158,7 @@ struct bcma_host_ops {
/* Chip IDs of SoCs */
#define BCMA_CHIP_ID_BCM4706 0x5300
#define BCMA_CHIP_ID_BCM4716 0x4716
#define BCMA_PKG_ID_BCM4716 8
#define BCMA_PKG_ID_BCM4717 9
-@@ -166,7 +167,11 @@ struct bcma_host_ops {
+@@ -166,7 +168,11 @@ struct bcma_host_ops {
#define BCMA_CHIP_ID_BCM4749 0x4749
#define BCMA_CHIP_ID_BCM5356 0x5356
#define BCMA_CHIP_ID_BCM5357 0x5357
struct bcma_device {
struct bcma_bus *bus;
-@@ -251,7 +256,7 @@ struct bcma_bus {
+@@ -251,7 +257,7 @@ struct bcma_bus {
u8 num;
struct bcma_drv_cc drv_cc;
struct bcma_drv_mips drv_mips;
struct bcma_drv_gmac_cmn drv_gmac_cmn;
-@@ -345,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
+@@ -345,6 +351,7 @@ extern void bcma_core_set_clockmode(stru
enum bcma_clkmode clkmode);
extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
bool on);
/* 0x1E0 is defined as shared BCMA_CLKCTLST */
#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
#define BCMA_CC_UART0_DATA 0x0300
-@@ -325,6 +353,60 @@
+@@ -288,6 +316,9 @@
+ #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
+ #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
+ #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
++#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
++#define BCMA_CC_PMU_CTL_RES_SHIFT 13
++#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
+ #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
+ #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
+ #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
+@@ -325,6 +356,60 @@
#define BCMA_CC_PLLCTL_ADDR 0x0660
#define BCMA_CC_PLLCTL_DATA 0x0664
#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
/* Divider allocation in 4716/47162/5356 */
#define BCMA_CC_PMU5_MAINPLL_CPU 1
-@@ -415,6 +497,13 @@
+@@ -415,6 +500,13 @@
/* 4313 Chip specific ChipControl register bits */
#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
/* Data for the PMU, if available.
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
*/
-@@ -425,11 +514,35 @@ struct bcma_chipcommon_pmu {
+@@ -425,11 +517,35 @@ struct bcma_chipcommon_pmu {
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash {
struct bcma_serial_port {
void *regs;
unsigned long clockspeed;
-@@ -445,15 +558,30 @@ struct bcma_drv_cc {
+@@ -445,15 +561,30 @@ struct bcma_drv_cc {
u32 capabilities;
u32 capabilities_ext;
u8 setup_done:1;
};
/* Register access */
-@@ -470,14 +598,16 @@ struct bcma_drv_cc {
+@@ -470,14 +601,16 @@ struct bcma_drv_cc {
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
-@@ -490,9 +620,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
+@@ -490,9 +623,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
/* Is there any BCM4328 on BCMA bus? */
#define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
#define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
-@@ -83,4 +85,9 @@
+@@ -35,6 +37,7 @@
+ #define BCMA_IOST_BIST_DONE 0x8000
+ #define BCMA_RESET_CTL 0x0800
+ #define BCMA_RESET_CTL_RESET 0x0001
++#define BCMA_RESET_ST 0x0804
+
+ /* BCMA PCI config space registers. */
+ #define BCMA_PCI_PMCSR 0x44
+@@ -83,4 +86,9 @@
* (2 ZettaBytes), high 32 bits
*/
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -682,6 +682,7 @@
+@@ -668,6 +668,7 @@ static const struct spi_device_id m25p_i
/* PMC -- pm25x "blocks" are 32K, sectors are 4K */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
/****************************************************************************/
struct m25p {
-@@ -903,7 +909,7 @@ static int __devinit m25p_probe(struct s
+@@ -904,7 +910,7 @@ static int __devinit m25p_probe(struct s
flash->mtd._write = m25p80_write;
/* prefer "small sector" erase if possible */
--- a/mm/shmem.c
+++ b/mm/shmem.c
-@@ -2914,6 +2914,16 @@ EXPORT_SYMBOL_GPL(shmem_truncate_range);
+@@ -2920,6 +2920,16 @@ EXPORT_SYMBOL_GPL(shmem_truncate_range);
/* common code */
/**
* shmem_file_setup - get an unlinked file living in tmpfs
* @name: name for dentry (to be seen in /proc/<pid>/maps
-@@ -2991,11 +3001,8 @@ int shmem_zero_setup(struct vm_area_stru
+@@ -2997,11 +3007,8 @@ int shmem_zero_setup(struct vm_area_stru
if (IS_ERR(file))
return PTR_ERR(file);
+}
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
-@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
+@@ -178,9 +178,9 @@ static void ssb_mips_serial_init(struct
{
struct ssb_bus *bus = mcore->dev->bus;
bcma_cc_write32(cc, BCMA_CC_CORECTL,
--- a/drivers/bcma/driver_chipcommon_nflash.c
+++ b/drivers/bcma/driver_chipcommon_nflash.c
-@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
+@@ -32,6 +32,9 @@ int bcma_nflash_init(struct bcma_drv_cc
}
cc->nflash.present = true;
void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
{
-@@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct
+@@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct
}
}
{ 0 },
};
-@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
+@@ -84,6 +111,8 @@ int bcma_sflash_init(struct bcma_drv_cc
break;
}
break;
default:
for (e = bcma_sflash_st_tbl; e->name; e++) {
if (e->id == id)
-@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
+@@ -116,7 +145,7 @@ int bcma_sflash_init(struct bcma_drv_cc
return -ENOTSUPP;
}
for (i = 0; i <= 6; i++)
printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
printk("\n");
-@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
+@@ -171,7 +194,7 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
struct bcma_bus *bus = mcore->core->bus;
if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU)
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
-@@ -157,6 +157,7 @@ struct bcma_host_ops {
+@@ -134,6 +134,7 @@ struct bcma_host_ops {
+ #define BCMA_CORE_I2S 0x834
+ #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
+ #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
++#define BCMA_CORE_ARM_CR4 0x83e
+ #define BCMA_CORE_DEFAULT 0xFFF
+
+ #define BCMA_MAX_NR_CORES 16
+@@ -157,6 +158,7 @@ struct bcma_host_ops {
/* Chip IDs of SoCs */
#define BCMA_CHIP_ID_BCM4706 0x5300
#define BCMA_CHIP_ID_BCM4716 0x4716
#define BCMA_PKG_ID_BCM4716 8
#define BCMA_PKG_ID_BCM4717 9
-@@ -166,7 +167,11 @@ struct bcma_host_ops {
+@@ -166,7 +168,11 @@ struct bcma_host_ops {
#define BCMA_CHIP_ID_BCM4749 0x4749
#define BCMA_CHIP_ID_BCM5356 0x5356
#define BCMA_CHIP_ID_BCM5357 0x5357
struct bcma_device {
struct bcma_bus *bus;
-@@ -251,7 +256,7 @@ struct bcma_bus {
+@@ -251,7 +257,7 @@ struct bcma_bus {
u8 num;
struct bcma_drv_cc drv_cc;
struct bcma_drv_mips drv_mips;
struct bcma_drv_gmac_cmn drv_gmac_cmn;
-@@ -345,6 +350,7 @@ extern void bcma_core_set_clockmode(stru
+@@ -345,6 +351,7 @@ extern void bcma_core_set_clockmode(stru
enum bcma_clkmode clkmode);
extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
bool on);
#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
#define BCMA_CC_JCMD_START 0x80000000
#define BCMA_CC_JCMD_BUSY 0x80000000
-@@ -510,6 +514,7 @@ struct bcma_chipcommon_pmu {
+@@ -312,6 +316,9 @@
+ #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
+ #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
+ #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
++#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
++#define BCMA_CC_PMU_CTL_RES_SHIFT 13
++#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
+ #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
+ #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
+ #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
+@@ -510,6 +517,7 @@ struct bcma_chipcommon_pmu {
#ifdef CONFIG_BCMA_DRIVER_MIPS
struct bcma_pflash {
u8 buswidth;
u32 window;
u32 window_size;
-@@ -532,6 +537,7 @@ struct mtd_info;
+@@ -532,6 +540,7 @@ struct mtd_info;
struct bcma_nflash {
bool present;
struct mtd_info *mtd;
};
-@@ -552,6 +558,7 @@ struct bcma_drv_cc {
+@@ -552,6 +561,7 @@ struct bcma_drv_cc {
u32 capabilities;
u32 capabilities_ext;
u8 setup_done:1;
/* Fast Powerup Delay constant */
u16 fast_pwrup_delay;
struct bcma_chipcommon_pmu pmu;
-@@ -567,6 +574,14 @@ struct bcma_drv_cc {
+@@ -567,6 +577,14 @@ struct bcma_drv_cc {
int nr_serial_ports;
struct bcma_serial_port serial_ports[4];
#endif /* CONFIG_BCMA_DRIVER_MIPS */
};
/* Register access */
-@@ -583,14 +598,16 @@ struct bcma_drv_cc {
+@@ -583,14 +601,16 @@ struct bcma_drv_cc {
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
-@@ -603,9 +620,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
+@@ -603,9 +623,12 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value);
u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value);
extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
--- a/include/linux/bcma/bcma_regs.h
+++ b/include/linux/bcma/bcma_regs.h
-@@ -85,6 +85,9 @@
+@@ -37,6 +37,7 @@
+ #define BCMA_IOST_BIST_DONE 0x8000
+ #define BCMA_RESET_CTL 0x0800
+ #define BCMA_RESET_CTL_RESET 0x0001
++#define BCMA_RESET_ST 0x0804
+
+ /* BCMA PCI config space registers. */
+ #define BCMA_PCI_PMCSR 0x44
+@@ -85,6 +86,9 @@
* (2 ZettaBytes), high 32 bits
*/
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
-@@ -682,6 +682,7 @@
+@@ -676,6 +676,7 @@ static const struct spi_device_id m25p_i
/* PMC -- pm25x "blocks" are 32K, sectors are 4K */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
/****************************************************************************/
struct m25p {
-@@ -915,7 +921,7 @@ static int __devinit m25p_probe(struct s
+@@ -916,7 +922,7 @@ static int __devinit m25p_probe(struct s
flash->mtd._write = m25p80_write;
/* prefer "small sector" erase if possible */
#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
#define BCMA_CC_JCMD_START 0x80000000
#define BCMA_CC_JCMD_BUSY 0x80000000
-@@ -606,6 +607,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
+@@ -315,6 +316,9 @@
+ #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
+ #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
+ #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
++#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
++#define BCMA_CC_PMU_CTL_RES_SHIFT 13
++#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
+ #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
+ #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
+ #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
+@@ -606,6 +610,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
break;
default:
bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
+--- a/include/linux/bcma/bcma.h
++++ b/include/linux/bcma/bcma.h
+@@ -134,6 +134,7 @@ struct bcma_host_ops {
+ #define BCMA_CORE_I2S 0x834
+ #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
+ #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
++#define BCMA_CORE_ARM_CR4 0x83e
+ #define BCMA_CORE_DEFAULT 0xFFF
+
+ #define BCMA_MAX_NR_CORES 16
+--- a/include/linux/bcma/bcma_regs.h
++++ b/include/linux/bcma/bcma_regs.h
+@@ -37,6 +37,7 @@
+ #define BCMA_IOST_BIST_DONE 0x8000
+ #define BCMA_RESET_CTL 0x0800
+ #define BCMA_RESET_CTL_RESET 0x0001
++#define BCMA_RESET_ST 0x0804
+
+ /* BCMA PCI config space registers. */
+ #define BCMA_PCI_PMCSR 0x44
--- /dev/null
+--- a/include/linux/bcma/bcma.h
++++ b/include/linux/bcma/bcma.h
+@@ -134,6 +134,7 @@ struct bcma_host_ops {
+ #define BCMA_CORE_I2S 0x834
+ #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
+ #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
++#define BCMA_CORE_ARM_CR4 0x83e
+ #define BCMA_CORE_DEFAULT 0xFFF
+
+ #define BCMA_MAX_NR_CORES 16
+--- a/include/linux/bcma/bcma_regs.h
++++ b/include/linux/bcma/bcma_regs.h
+@@ -37,6 +37,7 @@
+ #define BCMA_IOST_BIST_DONE 0x8000
+ #define BCMA_RESET_CTL 0x0800
+ #define BCMA_RESET_CTL_RESET 0x0001
++#define BCMA_RESET_ST 0x0804
+
+ /* BCMA PCI config space registers. */
+ #define BCMA_PCI_PMCSR 0x44
+--- a/include/linux/bcma/bcma_driver_chipcommon.h
++++ b/include/linux/bcma/bcma_driver_chipcommon.h
+@@ -316,6 +316,9 @@
+ #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
+ #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
+ #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
++#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
++#define BCMA_CC_PMU_CTL_RES_SHIFT 13
++#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
+ #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
+ #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
+ #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
projects / openwrt / staging / jogo.git / commitdiff