unsigned int idle_bias_off:1; /* Use BIAS_OFF instead of STANDBY */
unsigned int cache_only:1; /* Suppress writes to hardware */
+ unsigned int cache_sync:1; /* Cache needs to be synced to hardware */
/* dapm */
u32 pop_time;
if (reg < codec->reg_cache_size)
cache[reg] = value;
- if (codec->cache_only)
+ if (codec->cache_only) {
+ codec->cache_sync = 1;
return 0;
+ }
ret = codec->hw_write(codec->control_data, data, 2);
if (ret == 2)
if (reg < codec->reg_cache_size)
cache[reg] = value;
- if (codec->cache_only)
+ if (codec->cache_only) {
+ codec->cache_sync = 1;
return 0;
+ }
ret = codec->hw_write(codec->control_data, data, 2);
if (ret == 2)
if (reg < codec->reg_cache_size)
cache[reg] = value;
- if (codec->cache_only)
+ if (codec->cache_only) {
+ codec->cache_sync = 1;
return 0;
+ }
if (codec->hw_write(codec->control_data, data, 2) == 2)
return 0;
if (!snd_soc_codec_volatile_register(codec, reg))
reg_cache[reg] = value;
- if (codec->cache_only)
+ if (codec->cache_only) {
+ codec->cache_sync = 1;
return 0;
+ }
if (codec->hw_write(codec->control_data, data, 3) == 3)
return 0;
if (reg < codec->reg_cache_size)
cache[reg] = value;
- if (codec->cache_only)
+ if (codec->cache_only) {
+ codec->cache_sync = 1;
return 0;
+ }
ret = codec->hw_write(codec->control_data, data, 3);
if (ret == 3)