/* Macros to access registers */
-/* Interrupt status clear (only bits set in mask) */
-#define RtdInterruptClear(dev) \
- readw(devpriv->las0+LAS0_CLEAR)
-
/* Interrupt clear mask */
#define RtdInterruptClearMask(dev, v) \
writew((devpriv->intClearMask = (v)), devpriv->las0+LAS0_CLEAR)
/* clear the interrupt */
RtdInterruptClearMask(dev, status);
- RtdInterruptClear(dev);
+ readw(devpriv->las0 + LAS0_CLEAR);
return IRQ_HANDLED;
abortTransfer:
/* clear the interrupt */
status = readw(devpriv->las0 + LAS0_IT);
RtdInterruptClearMask(dev, status);
- RtdInterruptClear(dev);
+ readw(devpriv->las0 + LAS0_CLEAR);
fifoStatus = readl(devpriv->las0 + LAS0_ADC);
DPRINTK
/* This doesn't seem to work. There is no way to clear an interrupt
that the priority controller has queued! */
RtdInterruptClearMask(dev, ~0); /* clear any existing flags */
- RtdInterruptClear(dev);
+ readw(devpriv->las0 + LAS0_CLEAR);
/* TODO: allow multiple interrupt sources */
if (devpriv->transCount > 0) { /* transfer every N samples */
devpriv->intMask = 0;
writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
RtdInterruptClearMask(dev, ~0); /* and sets shadow */
- RtdInterruptClear(dev); /* clears bits set by mask */
+ readw(devpriv->las0 + LAS0_CLEAR);
RtdInterruptOverrunClear(dev);
writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
devpriv->intMask = 0;
writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
RtdInterruptClearMask(dev, ~0);
- RtdInterruptClear(dev); /* clears bits set by mask */
+ readw(devpriv->las0 + LAS0_CLEAR);
}
#ifdef USE_DMA
/* release DMA */