ice: Limit Max TCs on devices with more than 4 ports
authorUsha Ketineni <usha.k.ketineni@intel.com>
Thu, 8 Aug 2019 14:39:24 +0000 (07:39 -0700)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Tue, 3 Sep 2019 23:35:58 +0000 (16:35 -0700)
This patch limits the max TCs set by the driver to the value provided by
the firmware as per the capabilities of the device. Otherwise, hard coding
to 8 TC max would fail the device configurations with more than 4 ports.

Signed-off-by: Usha Ketineni <usha.k.ketineni@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
drivers/net/ethernet/intel/ice/ice_common.c
drivers/net/ethernet/intel/ice/ice_dcb_lib.c
drivers/net/ethernet/intel/ice/ice_type.h

index 8ebc695171b67fe0731455b4f11962f468d58b59..4da0cde9695bf871b222a12a4b938fa90ca879c3 100644 (file)
@@ -91,6 +91,7 @@ struct ice_aqc_list_caps_elem {
 #define ICE_AQC_CAPS_SRIOV                             0x0012
 #define ICE_AQC_CAPS_VF                                        0x0013
 #define ICE_AQC_CAPS_VSI                               0x0017
+#define ICE_AQC_CAPS_DCB                               0x0018
 #define ICE_AQC_CAPS_RSS                               0x0040
 #define ICE_AQC_CAPS_RXQS                              0x0041
 #define ICE_AQC_CAPS_TXQS                              0x0042
index 6c0abb284c103d9c95ccd80d20fd0ba912f0f8ef..9492cd34b09dc064da07c012a5a9122cee6aee6c 100644 (file)
@@ -1594,6 +1594,18 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
                                          prefix, func_p->guar_num_vsi);
                        }
                        break;
+               case ICE_AQC_CAPS_DCB:
+                       caps->dcb = (number == 1);
+                       caps->active_tc_bitmap = logical_id;
+                       caps->maxtc = phys_id;
+                       ice_debug(hw, ICE_DBG_INIT,
+                                 "%s: DCB = %d\n", prefix, caps->dcb);
+                       ice_debug(hw, ICE_DBG_INIT,
+                                 "%s: active TC bitmap = %d\n", prefix,
+                                 caps->active_tc_bitmap);
+                       ice_debug(hw, ICE_DBG_INIT,
+                                 "%s: TC max = %d\n", prefix, caps->maxtc);
+                       break;
                case ICE_AQC_CAPS_RSS:
                        caps->rss_table_size = number;
                        caps->rss_table_entry_width = logical_id;
index d9578919aad8203eb8c4331695903acba835d8ba..4614ec95529b2d89a9bca4a69301cbb221c40e38 100644 (file)
@@ -413,7 +413,7 @@ static int ice_dcb_sw_dflt_cfg(struct ice_pf *pf, bool locked)
        memset(&pi->local_dcbx_cfg, 0, sizeof(*dcbcfg));
 
        dcbcfg->etscfg.willing = 1;
-       dcbcfg->etscfg.maxtcs = 8;
+       dcbcfg->etscfg.maxtcs = hw->func_caps.common_cap.maxtc;
        dcbcfg->etscfg.tcbwtable[0] = 100;
        dcbcfg->etscfg.tsatable[0] = ICE_IEEE_TSA_ETS;
 
@@ -422,7 +422,7 @@ static int ice_dcb_sw_dflt_cfg(struct ice_pf *pf, bool locked)
        dcbcfg->etsrec.willing = 0;
 
        dcbcfg->pfc.willing = 1;
-       dcbcfg->pfc.pfccap = IEEE_8021QAZ_MAX_TCS;
+       dcbcfg->pfc.pfccap = hw->func_caps.common_cap.maxtc;
 
        dcbcfg->numapps = 1;
        dcbcfg->app[0].selector = ICE_APP_SEL_ETHTYPE;
@@ -454,6 +454,9 @@ int ice_init_pf_dcb(struct ice_pf *pf, bool locked)
        err = ice_init_dcb(hw);
        if (err) {
                /* FW LLDP is disabled, activate SW DCBX/LLDP mode */
+               dev_info(&pf->pdev->dev,
+                        "DCB is enabled in the hardware, max number of TCs supported on this port are %d\n",
+                        pf->hw.func_caps.common_cap.maxtc);
                dev_info(&pf->pdev->dev,
                         "FW LLDP is disabled, DCBx/LLDP in SW mode.\n");
                port_info->is_sw_lldp = true;
@@ -484,6 +487,9 @@ int ice_init_pf_dcb(struct ice_pf *pf, bool locked)
        if (err)
                goto dcb_init_err;
 
+       dev_info(&pf->pdev->dev,
+                "DCB is enabled in the hardware, max number of TCs supported on this port are %d\n",
+                pf->hw.func_caps.common_cap.maxtc);
        dev_info(&pf->pdev->dev, "DCBX offload supported\n");
        return err;
 
index 40b028e73234ee12a88398415c5b001a3ea70d47..4501d50a7dcc6c70d703e8a7d86c059afde27eb7 100644 (file)
@@ -139,6 +139,9 @@ struct ice_phy_info {
 /* Common HW capabilities for SW use */
 struct ice_hw_common_caps {
        u32 valid_functions;
+       /* DCB capabilities */
+       u32 active_tc_bitmap;
+       u32 maxtc;
 
        /* Tx/Rx queues */
        u16 num_rxq;            /* Number/Total Rx queues */