Enable secure timer to generate S-EL1 interrupts

This patch enables secure physical timer during TSP initialisation and
maintains it across power management operations so that a timer
interrupt is generated every half second.

Fixes ARM-software/tf-issues#104
Fixes ARM-software/tf-issues#134

Change-Id: I66c6cfd24bd5e6035ba75ebf0f047e568770a369

diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index dff67d5acefd8709f1b9fbf1c5135cc9df477982..ec74db428e38f9e9aad640e5e900e1dddef3559c 100644 (file)
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -128,6 +128,7 @@ uint64_t tsp_main(void)
        bl32_platform_setup();
 
        /* Initialize secure/applications state here */
+       tsp_generic_timer_start();
 
        /* Update this cpu's statistics */
        tsp_stats[linear_id].smc_count++;
@@ -163,6 +164,9 @@ tsp_args_t *tsp_cpu_on_main(void)
        uint64_t mpidr = read_mpidr();
        uint32_t linear_id = platform_get_core_pos(mpidr);
 
+       /* Initialize secure/applications state here */
+       tsp_generic_timer_start();
+
        /* Update this cpu's statistics */
        tsp_stats[linear_id].smc_count++;
        tsp_stats[linear_id].eret_count++;
@@ -196,6 +200,13 @@ tsp_args_t *tsp_cpu_off_main(uint64_t arg0,
        uint64_t mpidr = read_mpidr();
        uint32_t linear_id = platform_get_core_pos(mpidr);
 
+       /*
+        * This cpu is being turned off, so disable the timer to prevent the
+        * secure timer interrupt from interfering with power down. A pending
+        * interrupt will be lost but we do not care as we are turning off.
+        */
+       tsp_generic_timer_stop();
+
        /* Update this cpu's statistics */
        tsp_stats[linear_id].smc_count++;
        tsp_stats[linear_id].eret_count++;
@@ -231,6 +242,13 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t power_state,
        uint64_t mpidr = read_mpidr();
        uint32_t linear_id = platform_get_core_pos(mpidr);
 
+       /*
+        * Save the time context and disable it to prevent the secure timer
+        * interrupt from interfering with wakeup from the suspend state.
+        */
+       tsp_generic_timer_save();
+       tsp_generic_timer_stop();
+
        /* Update this cpu's statistics */
        tsp_stats[linear_id].smc_count++;
        tsp_stats[linear_id].eret_count++;
@@ -266,6 +284,9 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
        uint64_t mpidr = read_mpidr();
        uint32_t linear_id = platform_get_core_pos(mpidr);
 
+       /* Restore the generic timer context */
+       tsp_generic_timer_restore();
+
        /* Update this cpu's statistics */
        tsp_stats[linear_id].smc_count++;
        tsp_stats[linear_id].eret_count++;