drm/amd/display: Add MPC 3DLUT resource management

[Why & How]
Number of 3DLUT's in MPC are not equal to number of pipes.
Resource management is required.
Activate on FPGA entire tm solution  which includes
the following :hdr multiplier, shaper, 3dlut.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Gary Kattan <Gary.Kattan@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index f40e4fd52fa2ff13ede69485a125fcf4869c9293..b9d6a5bd8522aca3f17148d5960bf285e8814d98 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -60,7 +60,6 @@ static void construct(struct dc_context *ctx, struct dc_plane_state *plane_state
        plane_state->lut3d_func = dc_create_3dlut_func();
        if (plane_state->lut3d_func != NULL) {
                plane_state->lut3d_func->ctx = ctx;
-               plane_state->lut3d_func->initialized = false;
        }
        plane_state->blend_tf = dc_create_transfer_func();
        if (plane_state->blend_tf != NULL) {
@@ -279,7 +278,7 @@ struct dc_3dlut *dc_create_3dlut_func(void)
                goto alloc_fail;
 
        kref_init(&lut->refcount);
-       lut->initialized = false;
+       lut->state.raw = 0;
 
        return lut;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 786f61eb381db10e5f712685f31aa062a9dd8b62..421932ac3b267e93d5c4122abb6d82298cb44f8d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -616,12 +616,26 @@ struct dc_transfer_func {
 
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 
+union dc_3dlut_state {
+       struct {
+               uint32_t initialized:1;         /*if 3dlut is went through color module for initialization */
+               uint32_t rmu_idx_valid:1;       /*if mux settings are valid*/
+               uint32_t rmu_mux_num:3;         /*index of mux to use*/
+               uint32_t mpc_rmu0_mux:4;        /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
+               uint32_t mpc_rmu1_mux:4;
+               uint32_t mpc_rmu2_mux:4;
+               uint32_t reserved:15;
+       } bits;
+       uint32_t raw;
+};
+
 
 struct dc_3dlut {
        struct kref refcount;
        struct tetrahedral_params lut_3d;
        uint32_t hdr_multiplier;
-       bool initialized;
+       bool initialized; /*remove after diag fix*/
+       union dc_3dlut_state state;
        struct dc_context *ctx;
 };
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 9daab57a96eaa0aff94be7db8d071b5a808f7470..64ebfdbbba9bffa6bcd20433441a5bba133aa6d4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -952,14 +952,14 @@ static bool dcn20_set_shaper_3dlut(
 
        result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
        if (plane_state->lut3d_func &&
-               plane_state->lut3d_func->initialized == true)
+               plane_state->lut3d_func->state.bits.initialized == 1)
                result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
                                                                &plane_state->lut3d_func->lut_3d);
        else
                result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 
        if (plane_state->lut3d_func &&
-               plane_state->lut3d_func->initialized == true &&
+               plane_state->lut3d_func->state.bits.initialized == 1 &&
                plane_state->lut3d_func->hdr_multiplier != 0)
                dpp_base->funcs->dpp_set_hdr_multiplier(dpp_base,
                                plane_state->lut3d_func->hdr_multiplier);