priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
+
+ if (new_pos != pos)
+ new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
}
- if (new_pos != pos) {
- new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
- priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
+ if (pdata->sgmii_cfg) {
+ t = pdata->sgmii_cfg->sgmii_ctrl;
+ if (priv->chip_rev == 1)
+ t |= AR8327_SGMII_CTRL_EN_PLL |
+ AR8327_SGMII_CTRL_EN_RX |
+ AR8327_SGMII_CTRL_EN_TX;
+ else
+ t &= ~(AR8327_SGMII_CTRL_EN_PLL |
+ AR8327_SGMII_CTRL_EN_RX |
+ AR8327_SGMII_CTRL_EN_TX);
+
+ priv->write(priv, AR8327_REG_SGMII_CTRL, t);
+
+ if (pdata->sgmii_cfg->serdes_aen)
+ new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
+ else
+ new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
}
+ priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
+
return 0;
}
#define AR8327_REG_POWER_ON_STRIP 0x010
#define AR8327_POWER_ON_STRIP_POWER_ON_SEL BIT(31)
#define AR8327_POWER_ON_STRIP_LED_OPEN_EN BIT(24)
+#define AR8327_POWER_ON_STRIP_SERDES_AEN BIT(7)
#define AR8327_REG_INT_STATUS0 0x020
#define AR8327_INT0_VT_DONE BIT(20)
#define AR8327_REG_HEADER_CTRL 0x098
#define AR8327_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
+#define AR8327_REG_SGMII_CTRL 0x0e0
+#define AR8327_SGMII_CTRL_EN_PLL BIT(1)
+#define AR8327_SGMII_CTRL_EN_RX BIT(2)
+#define AR8327_SGMII_CTRL_EN_TX BIT(3)
+
#define AR8327_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
#define AR8327_PORT_VLAN0_DEF_SVID BITS(0, 12)
#define AR8327_PORT_VLAN0_DEF_SVID_S 0
int duplex:1;
};
+struct ar8327_sgmii_cfg {
+ u32 sgmii_ctrl;
+ bool serdes_aen;
+};
+
struct ar8327_led_cfg {
u32 led_ctrl0;
u32 led_ctrl1;
struct ar8327_pad_cfg *pad0_cfg;
struct ar8327_pad_cfg *pad5_cfg;
struct ar8327_pad_cfg *pad6_cfg;
+ struct ar8327_sgmii_cfg *sgmii_cfg;
struct ar8327_port_cfg port0_cfg;
struct ar8327_port_cfg port6_cfg;
struct ar8327_led_cfg *led_cfg;