drm/amd/display: Use plane->color_space for dpp if specified

[Why]
The input color space for the plane was previously ignored even if it
was set.

If a limited range YUV format was given to DC then the
wrong color transformation matrix was being used since DC assumed that
it was full range instead.

[How]
Respect the given color_space format for the plane if it isn't
COLOR_SPACE_UNKNOWN. Otherwise, use the implicit default since DM
didn't specify.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index f91e4b49d21131bd65479c98a4cd9ea3d7513749..6f4b24756323b152ddcf93ce71425943f2e9b4d9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -385,6 +385,10 @@ void dpp1_cnv_setup (
        default:
                break;
        }
+
+       /* Set default color space based on format if none is given. */
+       color_space = input_color_space ? input_color_space : color_space;
+
        REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
                        CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
        REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
@@ -396,7 +400,7 @@ void dpp1_cnv_setup (
                for (i = 0; i < 12; i++)
                        tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
 
-               tbl_entry.color_space = input_color_space;
+               tbl_entry.color_space = color_space;
 
                if (color_space >= COLOR_SPACE_YCBCR601)
                        select = INPUT_CSC_SELECT_ICSC;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 4969fa5e6f1dd2f6190dab9e00e82bb02a9bd443..976812ae4edeb4508ab7e8b60e068af72c3f2301 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1949,7 +1949,7 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
                        plane_state->format,
                        EXPANSION_MODE_ZERO,
                        plane_state->input_csc_color_matrix,
-                       COLOR_SPACE_YCBCR601_LIMITED);
+                       plane_state->color_space);
 
        //set scale and bias registers
        build_prescale_params(&bns_params, plane_state);