powerpc/mpc85xx: Add workaround for DDR erratum A004934

After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ce5924bc1327f9427c37e79b86bb07feb44c6dc1..2be192d578f5ae46818451c459b23203b974d38a 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -133,6 +133,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
        puts("Work-around for Erratum SRIO-A004034 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+       puts("Work-around for Erratum A004934 enabled\n");
 #endif
        return 0;
 }

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 8bed5fe925b8130ecc1d14aba850881c8242fa02..21840bfc2a8abecd4aa77785eda4badbd358d36d 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -140,6 +140,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                        out_be32(&ddr->debug[i], regs->debug[i]);
                }
        }
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+       out_be32(&ddr->debug[28], 0x00003000);
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
        out_be32(&ddr->debug[12], 0x00000015);

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index ecb156619da30bc5c4e4526a8d5b9f66bab5e136..92ca2ad74d174f2c8123420fb2de677503286340 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -512,6 +512,7 @@
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 
 #elif defined(CONFIG_PPC_B4860)