drm/amd/pp: Update clk with od setting when set power state

This can fix the issue resume from S3, the user's OD setting
were reverted to default.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 755f23511fc31ed3e9ba19632537648c163a68ff..6d93d52975ecb1f648ee0c2b837a70365613ee2c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3259,10 +3259,25 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
 {
        int result = 0;
        struct vega10_hwmgr *data = hwmgr->backend;
+       struct vega10_dpm_table *dpm_table = &data->dpm_table;
+       struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
+       struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
+       int count;
 
        if (!data->need_update_dpm_table)
                return 0;
 
+       if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+               for (count = 0; count < dpm_table->gfx_table.count; count++)
+                       dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
+       }
+
+       odn_clk_table = &odn_table->vdd_dep_on_mclk;
+       if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
+               for (count = 0; count < dpm_table->mem_table.count; count++)
+                       dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
+       }
+
        if (data->need_update_dpm_table &
                        (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK + DPMTABLE_UPDATE_SOCCLK)) {
                result = vega10_populate_all_graphic_levels(hwmgr);