drm/i915/perf: reuse timestamp frequency from device info

Now that we have this stored in the device info, we can drop it from perf
part of the driver.

Note that this requires to init perf after we've computed the frequency,
hence why we move i915_perf_init() from i915_driver_init_early() to after
intel_device_info_runtime_init().

v2: Use div_u64 (Chris)

v3: Drop u64 divs by switching to kHz (Chris/Ville)
    Move i915_perf_fini to i915_driver_cleanup_hw (Matthew)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113181902.12411-2-lionel.g.landwerlin@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 87452c5558d317e098239a923942618603465758..2b4ced93011b768f91269fd1ff3ae90bbb44905d 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -936,8 +936,6 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 
        intel_detect_preproduction_hw(dev_priv);
 
-       i915_perf_init(dev_priv);
-
        return 0;
 
 err_irq:
@@ -954,7 +952,6 @@ err_engines:
  */
 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 {
-       i915_perf_fini(dev_priv);
        i915_gem_load_cleanup(dev_priv);
        intel_irq_fini(dev_priv);
        i915_workqueues_cleanup(dev_priv);
@@ -1101,6 +1098,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 
        intel_sanitize_options(dev_priv);
 
+       i915_perf_init(dev_priv);
+
        ret = i915_ggtt_probe_hw(dev_priv);
        if (ret)
                return ret;
@@ -1206,6 +1205,8 @@ static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
 {
        struct pci_dev *pdev = dev_priv->drm.pdev;
 
+       i915_perf_fini(dev_priv);
+
        if (pdev->msi_enabled)
                pci_disable_msi(pdev);
 

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 36bb4927484a05489531fc30cf3d99bdf221cde0..2b766253f9706a80c98cccb500fb00a65cf4e6b9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2619,7 +2619,6 @@ struct drm_i915_private {
 
                        bool periodic;
                        int period_exponent;
-                       int timestamp_frequency;
 
                        struct i915_oa_config test_config;
 

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index fd150099978caa4bce6d1ecc4a084d337d6c026c..adbce839a918b0bbc906b4b42da53554681a4ec4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2690,8 +2690,8 @@ err:
 
 static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
 {
-       return div_u64(1000000000ULL * (2ULL << exponent),
-                      dev_priv->perf.oa.timestamp_frequency);
+       return div64_u64(1000000000ULL * (2ULL << exponent),
+                        1000ULL * INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz);
 }
 
 /**
@@ -3423,8 +3423,6 @@ static struct ctl_table dev_root[] = {
  */
 void i915_perf_init(struct drm_i915_private *dev_priv)
 {
-       dev_priv->perf.oa.timestamp_frequency = 0;
-
        if (IS_HASWELL(dev_priv)) {
                dev_priv->perf.oa.ops.is_valid_b_counter_reg =
                        gen7_is_valid_b_counter_addr;
@@ -3440,8 +3438,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
                dev_priv->perf.oa.ops.oa_hw_tail_read =
                        gen7_oa_hw_tail_read;
 
-               dev_priv->perf.oa.timestamp_frequency = 12500000;
-
                dev_priv->perf.oa.oa_formats = hsw_oa_formats;
        } else if (i915_modparams.enable_execlists) {
                /* Note: that although we could theoretically also support the
@@ -3485,23 +3481,6 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
 
                                dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
                        }
-
-                       switch (dev_priv->info.platform) {
-                       case INTEL_BROADWELL:
-                               dev_priv->perf.oa.timestamp_frequency = 12500000;
-                               break;
-                       case INTEL_BROXTON:
-                       case INTEL_GEMINILAKE:
-                               dev_priv->perf.oa.timestamp_frequency = 19200000;
-                               break;
-                       case INTEL_SKYLAKE:
-                       case INTEL_KABYLAKE:
-                       case INTEL_COFFEELAKE:
-                               dev_priv->perf.oa.timestamp_frequency = 12000000;
-                               break;
-                       default:
-                               break;
-                       }
                } else if (IS_GEN10(dev_priv)) {
                        dev_priv->perf.oa.ops.is_valid_b_counter_reg =
                                gen7_is_valid_b_counter_addr;
@@ -3517,15 +3496,10 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
                        dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
 
                        dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
-
-                       /* Default frequency, although we need to read it from
-                        * the register as it might vary between parts.
-                        */
-                       dev_priv->perf.oa.timestamp_frequency = 12000000;
                }
        }
 
-       if (dev_priv->perf.oa.timestamp_frequency) {
+       if (dev_priv->perf.oa.ops.enable_metric_set) {
                hrtimer_init(&dev_priv->perf.oa.poll_check_timer,
                                CLOCK_MONOTONIC, HRTIMER_MODE_REL);
                dev_priv->perf.oa.poll_check_timer.function = oa_poll_check_timer_cb;
@@ -3535,8 +3509,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
                mutex_init(&dev_priv->perf.lock);
                spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
 
-               oa_sample_rate_hard_limit =
-                       dev_priv->perf.oa.timestamp_frequency / 2;
+               oa_sample_rate_hard_limit = 1000 *
+                       (INTEL_INFO(dev_priv)->cs_timestamp_frequency_khz / 2);
                dev_priv->perf.sysctl_header = register_sysctl_table(dev_root);
 
                mutex_init(&dev_priv->perf.metrics_lock);