arm64: dts: qcom: Add 8x16 Serial UART1 node

This patch adds the nodes required to support the UART1 node on the
MSM8916 and also fixes the sleep pins function for UART2.

Signed-off-by: Andy Gross <agross@codeaurora.org>

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 66804ffbc6d29724f2bc5a83a869042ad7159f15..3fc3be447edd25c54adc8d6cb5fbf07ded9c04c1 100644 (file)
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -19,6 +19,7 @@
 / {
        aliases {
                serial0 = &blsp1_uart2;
+               serial1 = &blsp1_uart1;
        };
 
        chosen {

diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 568956859088c168573b1306ae4808a6de275e41..42941b977c487e63b5501cb808ef35d49b121fc7 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -13,6 +13,30 @@
 
 &msmgpio {
 
+       blsp1_uart1_default: blsp1_uart1_default {
+               pinmux {
+                       function = "blsp_uart1";
+                       pins = "gpio0", "gpio1";
+               };
+               pinconf {
+                       pins = "gpio0", "gpio1";
+                       drive-strength = <16>;
+                       bias-disable;
+               };
+       };
+
+       blsp1_uart1_sleep: blsp1_uart1_sleep {
+               pinmux {
+                       function = "gpio";
+                       pins = "gpio0", "gpio1";
+               };
+               pinconf {
+                       pins = "gpio0", "gpio1";
+                       drive-strength = <2>;
+                       bias-pull-down;
+               };
+       };
+
        blsp1_uart2_default: blsp1_uart2_default {
                pinmux {
                        function = "blsp_uart2";
@@ -27,7 +51,7 @@
 
        blsp1_uart2_sleep: blsp1_uart2_sleep {
                pinmux {
-                       function = "blsp_uart2";
+                       function = "gpio";
                        pins = "gpio4", "gpio5";
                };
                pinconf {

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 72be4baa8fe7ce50b4b1ccda311532d7e77735ef..85f7bee33c184f22d6e1e4d20f96b8c53d26dffd 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -102,6 +102,15 @@
                        reg = <0x1800000 0x80000>;
                };
 
+               blsp1_uart1: serial@78af000 {
+                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                       reg = <0x78af000 0x200>;
+                       interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
+                       clock-names = "core", "iface";
+                       status = "disabled";
+               };
+
                blsp1_uart2: serial@78b0000 {
                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
                        reg = <0x78b0000 0x200>;