macb: Move the Atmel driver
authorJeff Kirsher <jeffrey.t.kirsher@intel.com>
Sat, 18 Jun 2011 08:52:36 +0000 (01:52 -0700)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Fri, 12 Aug 2011 19:38:26 +0000 (12:38 -0700)
Move the Atmel driver into drivers/net/ethernet/cadence/ and
make the necessary Kconfig and Makefile changes.

CC: Nicolas Ferre <nicolas.ferre@atmel.com>
CC: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Acked-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
17 files changed:
MAINTAINERS
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/arm/Kconfig [deleted file]
drivers/net/arm/Makefile [deleted file]
drivers/net/arm/at91_ether.c [deleted file]
drivers/net/arm/at91_ether.h [deleted file]
drivers/net/ethernet/Kconfig
drivers/net/ethernet/Makefile
drivers/net/ethernet/cadence/Kconfig [new file with mode: 0644]
drivers/net/ethernet/cadence/Makefile [new file with mode: 0644]
drivers/net/ethernet/cadence/at91_ether.c [new file with mode: 0644]
drivers/net/ethernet/cadence/at91_ether.h [new file with mode: 0644]
drivers/net/ethernet/cadence/macb.c [new file with mode: 0644]
drivers/net/ethernet/cadence/macb.h [new file with mode: 0644]
drivers/net/macb.c [deleted file]
drivers/net/macb.h [deleted file]

index 15d70213be536ea88b1ee84e233ac0cfdee72153..ae60f8c7c65d987d3f167ba12ac912064623e5f9 100644 (file)
@@ -1323,7 +1323,7 @@ F:        include/video/atmel_lcdc.h
 ATMEL MACB ETHERNET DRIVER
 M:     Nicolas Ferre <nicolas.ferre@atmel.com>
 S:     Supported
-F:     drivers/net/macb.*
+F:     drivers/net/ethernet/cadence/
 
 ATMEL SPI DRIVER
 M:     Nicolas Ferre <nicolas.ferre@atmel.com>
index 10c25b5bb2fec4b621b51ce350eba7154b06e31a..3f6622c3f8069a8ac39b72db9d15ae493e31d233 100644 (file)
@@ -2,9 +2,6 @@
 # Network device configuration
 #
 
-config HAVE_NET_MACB
-       bool
-
 menuconfig NETDEVICES
        default y if UML
        depends on NET
@@ -224,19 +221,6 @@ menuconfig NET_ETHERNET
 
 if NET_ETHERNET
 
-config MACB
-       tristate "Atmel MACB support"
-       depends on HAVE_NET_MACB
-       select PHYLIB
-       help
-         The Atmel MACB ethernet interface is found on many AT32 and AT91
-         parts. Say Y to include support for the MACB chip.
-
-         To compile this driver as a module, choose M here: the module
-         will be called macb.
-
-source "drivers/net/arm/Kconfig"
-
 config SH_ETH
        tristate "Renesas SuperH Ethernet support"
        depends on SUPERH && \
index d249d76ce2f98d4b0039ac4aabdd8c5af574d1ce..d7873bad9ddd4590559dc5ace29c6280bfa30140 100644 (file)
@@ -63,9 +63,6 @@ obj-$(CONFIG_ETHOC) += ethoc.o
 obj-$(CONFIG_GRETH) += greth.o
 
 obj-$(CONFIG_DNET) += dnet.o
-obj-$(CONFIG_MACB) += macb.o
-
-obj-$(CONFIG_ARM) += arm/
 obj-$(CONFIG_DEV_APPLETALK) += appletalk/
 obj-$(CONFIG_ETHERNET) += ethernet/
 obj-$(CONFIG_TR) += tokenring/
diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
deleted file mode 100644 (file)
index 57d16b9..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Acorn Network device configuration
-#  These are for Acorn's Expansion card network interfaces
-#
-
-config ARM_AT91_ETHER
-       tristate "AT91RM9200 Ethernet support"
-       depends on ARM && ARCH_AT91RM9200
-       select MII
-       help
-         If you wish to compile a kernel for the AT91RM9200 and enable
-         ethernet support, then you should always answer Y to this.
diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile
deleted file mode 100644 (file)
index fc0f85c..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-# File: drivers/net/arm/Makefile
-#
-# Makefile for the ARM network device drivers
-#
-
-obj-$(CONFIG_ARM_AT91_ETHER)   += at91_ether.o
diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c
deleted file mode 100644 (file)
index 29dc435..0000000
+++ /dev/null
@@ -1,1254 +0,0 @@
-/*
- * Ethernet driver for the Atmel AT91RM9200 (Thunder)
- *
- *  Copyright (C) 2003 SAN People (Pty) Ltd
- *
- * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
- * Initial version by Rick Bronson 01/11/2003
- *
- * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
- *   (Polaroid Corporation)
- *
- * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/mii.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/dma-mapping.h>
-#include <linux/ethtool.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/gfp.h>
-
-#include <asm/io.h>
-#include <asm/uaccess.h>
-#include <asm/mach-types.h>
-
-#include <mach/at91rm9200_emac.h>
-#include <mach/gpio.h>
-#include <mach/board.h>
-
-#include "at91_ether.h"
-
-#define DRV_NAME       "at91_ether"
-#define DRV_VERSION    "1.0"
-
-#define LINK_POLL_INTERVAL     (HZ)
-
-/* ..................................................................... */
-
-/*
- * Read from a EMAC register.
- */
-static inline unsigned long at91_emac_read(unsigned int reg)
-{
-       void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
-
-       return __raw_readl(emac_base + reg);
-}
-
-/*
- * Write to a EMAC register.
- */
-static inline void at91_emac_write(unsigned int reg, unsigned long value)
-{
-       void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
-
-       __raw_writel(value, emac_base + reg);
-}
-
-/* ........................... PHY INTERFACE ........................... */
-
-/*
- * Enable the MDIO bit in MAC control register
- * When not called from an interrupt-handler, access to the PHY must be
- *  protected by a spinlock.
- */
-static void enable_mdi(void)
-{
-       unsigned long ctl;
-
-       ctl = at91_emac_read(AT91_EMAC_CTL);
-       at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE);    /* enable management port */
-}
-
-/*
- * Disable the MDIO bit in the MAC control register
- */
-static void disable_mdi(void)
-{
-       unsigned long ctl;
-
-       ctl = at91_emac_read(AT91_EMAC_CTL);
-       at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE);   /* disable management port */
-}
-
-/*
- * Wait until the PHY operation is complete.
- */
-static inline void at91_phy_wait(void) {
-       unsigned long timeout = jiffies + 2;
-
-       while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
-               if (time_after(jiffies, timeout)) {
-                       printk("at91_ether: MIO timeout\n");
-                       break;
-               }
-               cpu_relax();
-       }
-}
-
-/*
- * Write value to the a PHY register
- * Note: MDI interface is assumed to already have been enabled.
- */
-static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
-{
-       at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
-               | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
-
-       /* Wait until IDLE bit in Network Status register is cleared */
-       at91_phy_wait();
-}
-
-/*
- * Read value stored in a PHY register.
- * Note: MDI interface is assumed to already have been enabled.
- */
-static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
-{
-       at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
-               | ((phy_addr & 0x1f) << 23) | (address << 18));
-
-       /* Wait until IDLE bit in Network Status register is cleared */
-       at91_phy_wait();
-
-       *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
-}
-
-/* ........................... PHY MANAGEMENT .......................... */
-
-/*
- * Access the PHY to determine the current link speed and mode, and update the
- * MAC accordingly.
- * If no link or auto-negotiation is busy, then no changes are made.
- */
-static void update_linkspeed(struct net_device *dev, int silent)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       unsigned int bmsr, bmcr, lpa, mac_cfg;
-       unsigned int speed, duplex;
-
-       if (!mii_link_ok(&lp->mii)) {           /* no link */
-               netif_carrier_off(dev);
-               if (!silent)
-                       printk(KERN_INFO "%s: Link down.\n", dev->name);
-               return;
-       }
-
-       /* Link up, or auto-negotiation still in progress */
-       read_phy(lp->phy_address, MII_BMSR, &bmsr);
-       read_phy(lp->phy_address, MII_BMCR, &bmcr);
-       if (bmcr & BMCR_ANENABLE) {                             /* AutoNegotiation is enabled */
-               if (!(bmsr & BMSR_ANEGCOMPLETE))
-                       return;                 /* Do nothing - another interrupt generated when negotiation complete */
-
-               read_phy(lp->phy_address, MII_LPA, &lpa);
-               if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
-               else speed = SPEED_10;
-               if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
-               else duplex = DUPLEX_HALF;
-       } else {
-               speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
-               duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
-       }
-
-       /* Update the MAC */
-       mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
-       if (speed == SPEED_100) {
-               if (duplex == DUPLEX_FULL)              /* 100 Full Duplex */
-                       mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
-               else                                    /* 100 Half Duplex */
-                       mac_cfg |= AT91_EMAC_SPD;
-       } else {
-               if (duplex == DUPLEX_FULL)              /* 10 Full Duplex */
-                       mac_cfg |= AT91_EMAC_FD;
-               else {}                                 /* 10 Half Duplex */
-       }
-       at91_emac_write(AT91_EMAC_CFG, mac_cfg);
-
-       if (!silent)
-               printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
-       netif_carrier_on(dev);
-}
-
-/*
- * Handle interrupts from the PHY
- */
-static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
-{
-       struct net_device *dev = (struct net_device *) dev_id;
-       struct at91_private *lp = netdev_priv(dev);
-       unsigned int phy;
-
-       /*
-        * This hander is triggered on both edges, but the PHY chips expect
-        * level-triggering.  We therefore have to check if the PHY actually has
-        * an IRQ pending.
-        */
-       enable_mdi();
-       if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
-               read_phy(lp->phy_address, MII_DSINTR_REG, &phy);        /* ack interrupt in Davicom PHY */
-               if (!(phy & (1 << 0)))
-                       goto done;
-       }
-       else if (lp->phy_type == MII_LXT971A_ID) {
-               read_phy(lp->phy_address, MII_ISINTS_REG, &phy);        /* ack interrupt in Intel PHY */
-               if (!(phy & (1 << 2)))
-                       goto done;
-       }
-       else if (lp->phy_type == MII_BCM5221_ID) {
-               read_phy(lp->phy_address, MII_BCMINTR_REG, &phy);       /* ack interrupt in Broadcom PHY */
-               if (!(phy & (1 << 0)))
-                       goto done;
-       }
-       else if (lp->phy_type == MII_KS8721_ID) {
-               read_phy(lp->phy_address, MII_TPISTATUS, &phy);         /* ack interrupt in Micrel PHY */
-               if (!(phy & ((1 << 2) | 1)))
-                       goto done;
-       }
-       else if (lp->phy_type == MII_T78Q21x3_ID) {                     /* ack interrupt in Teridian PHY */
-               read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
-               if (!(phy & ((1 << 2) | 1)))
-                       goto done;
-       }
-       else if (lp->phy_type == MII_DP83848_ID) {
-               read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy);      /* ack interrupt in DP83848 PHY */
-               if (!(phy & (1 << 7)))
-                       goto done;
-       }
-
-       update_linkspeed(dev, 0);
-
-done:
-       disable_mdi();
-
-       return IRQ_HANDLED;
-}
-
-/*
- * Initialize and enable the PHY interrupt for link-state changes
- */
-static void enable_phyirq(struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       unsigned int dsintr, irq_number;
-       int status;
-
-       irq_number = lp->board_data.phy_irq_pin;
-       if (!irq_number) {
-               /*
-                * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
-                * or board does not have it connected.
-                */
-               mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
-               return;
-       }
-
-       status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
-       if (status) {
-               printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
-               return;
-       }
-
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-
-       if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {      /* for Davicom PHY */
-               read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
-               dsintr = dsintr & ~0xf00;               /* clear bits 8..11 */
-               write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
-       }
-       else if (lp->phy_type == MII_LXT971A_ID) {      /* for Intel PHY */
-               read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
-               dsintr = dsintr | 0xf2;                 /* set bits 1, 4..7 */
-               write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
-       }
-       else if (lp->phy_type == MII_BCM5221_ID) {      /* for Broadcom PHY */
-               dsintr = (1 << 15) | ( 1 << 14);
-               write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
-       }
-       else if (lp->phy_type == MII_KS8721_ID) {       /* for Micrel PHY */
-               dsintr = (1 << 10) | ( 1 << 8);
-               write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
-       }
-       else if (lp->phy_type == MII_T78Q21x3_ID) {     /* for Teridian PHY */
-               read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
-               dsintr = dsintr | 0x500;                /* set bits 8, 10 */
-               write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
-       }
-       else if (lp->phy_type == MII_DP83848_ID) {      /* National Semiconductor DP83848 PHY */
-               read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
-               dsintr = dsintr | 0x3c;                 /* set bits 2..5 */
-               write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
-               read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
-               dsintr = dsintr | 0x3;                  /* set bits 0,1 */
-               write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
-       }
-
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-}
-
-/*
- * Disable the PHY interrupt
- */
-static void disable_phyirq(struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       unsigned int dsintr;
-       unsigned int irq_number;
-
-       irq_number = lp->board_data.phy_irq_pin;
-       if (!irq_number) {
-               del_timer_sync(&lp->check_timer);
-               return;
-       }
-
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-
-       if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {      /* for Davicom PHY */
-               read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
-               dsintr = dsintr | 0xf00;                        /* set bits 8..11 */
-               write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
-       }
-       else if (lp->phy_type == MII_LXT971A_ID) {      /* for Intel PHY */
-               read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
-               dsintr = dsintr & ~0xf2;                        /* clear bits 1, 4..7 */
-               write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
-       }
-       else if (lp->phy_type == MII_BCM5221_ID) {      /* for Broadcom PHY */
-               read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
-               dsintr = ~(1 << 14);
-               write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
-       }
-       else if (lp->phy_type == MII_KS8721_ID) {       /* for Micrel PHY */
-               read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
-               dsintr = ~((1 << 10) | (1 << 8));
-               write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
-       }
-       else if (lp->phy_type == MII_T78Q21x3_ID) {     /* for Teridian PHY */
-               read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
-               dsintr = dsintr & ~0x500;                       /* clear bits 8, 10 */
-               write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
-       }
-       else if (lp->phy_type == MII_DP83848_ID) {      /* National Semiconductor DP83848 PHY */
-               read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
-               dsintr = dsintr & ~0x3;                         /* clear bits 0, 1 */
-               write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
-               read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
-               dsintr = dsintr & ~0x3c;                        /* clear bits 2..5 */
-               write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
-       }
-
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-
-       free_irq(irq_number, dev);                      /* Free interrupt handler */
-}
-
-/*
- * Perform a software reset of the PHY.
- */
-#if 0
-static void reset_phy(struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       unsigned int bmcr;
-
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-
-       /* Perform PHY reset */
-       write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
-
-       /* Wait until PHY reset is complete */
-       do {
-               read_phy(lp->phy_address, MII_BMCR, &bmcr);
-       } while (!(bmcr & BMCR_RESET));
-
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-}
-#endif
-
-static void at91ether_check_link(unsigned long dev_id)
-{
-       struct net_device *dev = (struct net_device *) dev_id;
-       struct at91_private *lp = netdev_priv(dev);
-
-       enable_mdi();
-       update_linkspeed(dev, 1);
-       disable_mdi();
-
-       mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
-}
-
-/* ......................... ADDRESS MANAGEMENT ........................ */
-
-/*
- * NOTE: Your bootloader must always set the MAC address correctly before
- * booting into Linux.
- *
- * - It must always set the MAC address after reset, even if it doesn't
- *   happen to access the Ethernet while it's booting.  Some versions of
- *   U-Boot on the AT91RM9200-DK do not do this.
- *
- * - Likewise it must store the addresses in the correct byte order.
- *   MicroMonitor (uMon) on the CSB337 does this incorrectly (and
- *   continues to do so, for bug-compatibility).
- */
-
-static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
-{
-       char addr[6];
-
-       if (machine_is_csb337()) {
-               addr[5] = (lo & 0xff);                  /* The CSB337 bootloader stores the MAC the wrong-way around */
-               addr[4] = (lo & 0xff00) >> 8;
-               addr[3] = (lo & 0xff0000) >> 16;
-               addr[2] = (lo & 0xff000000) >> 24;
-               addr[1] = (hi & 0xff);
-               addr[0] = (hi & 0xff00) >> 8;
-       }
-       else {
-               addr[0] = (lo & 0xff);
-               addr[1] = (lo & 0xff00) >> 8;
-               addr[2] = (lo & 0xff0000) >> 16;
-               addr[3] = (lo & 0xff000000) >> 24;
-               addr[4] = (hi & 0xff);
-               addr[5] = (hi & 0xff00) >> 8;
-       }
-
-       if (is_valid_ether_addr(addr)) {
-               memcpy(dev->dev_addr, &addr, 6);
-               return 1;
-       }
-       return 0;
-}
-
-/*
- * Set the ethernet MAC address in dev->dev_addr
- */
-static void __init get_mac_address(struct net_device *dev)
-{
-       /* Check Specific-Address 1 */
-       if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
-               return;
-       /* Check Specific-Address 2 */
-       if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
-               return;
-       /* Check Specific-Address 3 */
-       if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
-               return;
-       /* Check Specific-Address 4 */
-       if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
-               return;
-
-       printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
-}
-
-/*
- * Program the hardware MAC address from dev->dev_addr.
- */
-static void update_mac_address(struct net_device *dev)
-{
-       at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
-       at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
-
-       at91_emac_write(AT91_EMAC_SA2L, 0);
-       at91_emac_write(AT91_EMAC_SA2H, 0);
-}
-
-/*
- * Store the new hardware address in dev->dev_addr, and update the MAC.
- */
-static int set_mac_address(struct net_device *dev, void* addr)
-{
-       struct sockaddr *address = addr;
-
-       if (!is_valid_ether_addr(address->sa_data))
-               return -EADDRNOTAVAIL;
-
-       memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
-       update_mac_address(dev);
-
-       printk("%s: Setting MAC address to %pM\n", dev->name,
-              dev->dev_addr);
-
-       return 0;
-}
-
-static int inline hash_bit_value(int bitnr, __u8 *addr)
-{
-       if (addr[bitnr / 8] & (1 << (bitnr % 8)))
-               return 1;
-       return 0;
-}
-
-/*
- * The hash address register is 64 bits long and takes up two locations in the memory map.
- * The least significant bits are stored in EMAC_HSL and the most significant
- * bits in EMAC_HSH.
- *
- * The unicast hash enable and the multicast hash enable bits in the network configuration
- *  register enable the reception of hash matched frames. The destination address is
- *  reduced to a 6 bit index into the 64 bit hash register using the following hash function.
- * The hash function is an exclusive or of every sixth bit of the destination address.
- *   hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
- *   hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
- *   hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
- *   hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
- *   hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
- *   hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
- * da[0] represents the least significant bit of the first byte received, that is, the multicast/
- *  unicast indicator, and da[47] represents the most significant bit of the last byte
- *  received.
- * If the hash index points to a bit that is set in the hash register then the frame will be
- *  matched according to whether the frame is multicast or unicast.
- * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
- *  the hash index points to a bit set in the hash register.
- * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
- *  hash index points to a bit set in the hash register.
- * To receive all multicast frames, the hash register should be set with all ones and the
- *  multicast hash enable bit should be set in the network configuration register.
- */
-
-/*
- * Return the hash index value for the specified address.
- */
-static int hash_get_index(__u8 *addr)
-{
-       int i, j, bitval;
-       int hash_index = 0;
-
-       for (j = 0; j < 6; j++) {
-               for (i = 0, bitval = 0; i < 8; i++)
-                       bitval ^= hash_bit_value(i*6 + j, addr);
-
-               hash_index |= (bitval << j);
-       }
-
-       return hash_index;
-}
-
-/*
- * Add multicast addresses to the internal multicast-hash table.
- */
-static void at91ether_sethashtable(struct net_device *dev)
-{
-       struct netdev_hw_addr *ha;
-       unsigned long mc_filter[2];
-       unsigned int bitnr;
-
-       mc_filter[0] = mc_filter[1] = 0;
-
-       netdev_for_each_mc_addr(ha, dev) {
-               bitnr = hash_get_index(ha->addr);
-               mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
-       }
-
-       at91_emac_write(AT91_EMAC_HSL, mc_filter[0]);
-       at91_emac_write(AT91_EMAC_HSH, mc_filter[1]);
-}
-
-/*
- * Enable/Disable promiscuous and multicast modes.
- */
-static void at91ether_set_multicast_list(struct net_device *dev)
-{
-       unsigned long cfg;
-
-       cfg = at91_emac_read(AT91_EMAC_CFG);
-
-       if (dev->flags & IFF_PROMISC)                   /* Enable promiscuous mode */
-               cfg |= AT91_EMAC_CAF;
-       else if (dev->flags & (~IFF_PROMISC))           /* Disable promiscuous mode */
-               cfg &= ~AT91_EMAC_CAF;
-
-       if (dev->flags & IFF_ALLMULTI) {                /* Enable all multicast mode */
-               at91_emac_write(AT91_EMAC_HSH, -1);
-               at91_emac_write(AT91_EMAC_HSL, -1);
-               cfg |= AT91_EMAC_MTI;
-       } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */
-               at91ether_sethashtable(dev);
-               cfg |= AT91_EMAC_MTI;
-       } else if (dev->flags & (~IFF_ALLMULTI)) {      /* Disable all multicast mode */
-               at91_emac_write(AT91_EMAC_HSH, 0);
-               at91_emac_write(AT91_EMAC_HSL, 0);
-               cfg &= ~AT91_EMAC_MTI;
-       }
-
-       at91_emac_write(AT91_EMAC_CFG, cfg);
-}
-
-/* ......................... ETHTOOL SUPPORT ........................... */
-
-static int mdio_read(struct net_device *dev, int phy_id, int location)
-{
-       unsigned int value;
-
-       read_phy(phy_id, location, &value);
-       return value;
-}
-
-static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
-{
-       write_phy(phy_id, location, value);
-}
-
-static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       int ret;
-
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-
-       ret = mii_ethtool_gset(&lp->mii, cmd);
-
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-
-       if (lp->phy_media == PORT_FIBRE) {              /* override media type since mii.c doesn't know */
-               cmd->supported = SUPPORTED_FIBRE;
-               cmd->port = PORT_FIBRE;
-       }
-
-       return ret;
-}
-
-static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       int ret;
-
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-
-       ret = mii_ethtool_sset(&lp->mii, cmd);
-
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-
-       return ret;
-}
-
-static int at91ether_nwayreset(struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       int ret;
-
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-
-       ret = mii_nway_restart(&lp->mii);
-
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-
-       return ret;
-}
-
-static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
-{
-       strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
-       strlcpy(info->version, DRV_VERSION, sizeof(info->version));
-       strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
-}
-
-static const struct ethtool_ops at91ether_ethtool_ops = {
-       .get_settings   = at91ether_get_settings,
-       .set_settings   = at91ether_set_settings,
-       .get_drvinfo    = at91ether_get_drvinfo,
-       .nway_reset     = at91ether_nwayreset,
-       .get_link       = ethtool_op_get_link,
-};
-
-static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       int res;
-
-       if (!netif_running(dev))
-               return -EINVAL;
-
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-       res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-
-       return res;
-}
-
-/* ................................ MAC ................................ */
-
-/*
- * Initialize and start the Receiver and Transmit subsystems
- */
-static void at91ether_start(struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       struct recv_desc_bufs *dlist, *dlist_phys;
-       int i;
-       unsigned long ctl;
-
-       dlist = lp->dlist;
-       dlist_phys = lp->dlist_phys;
-
-       for (i = 0; i < MAX_RX_DESCR; i++) {
-               dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
-               dlist->descriptors[i].size = 0;
-       }
-
-       /* Set the Wrap bit on the last descriptor */
-       dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
-
-       /* Reset buffer index */
-       lp->rxBuffIndex = 0;
-
-       /* Program address of descriptor list in Rx Buffer Queue register */
-       at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
-
-       /* Enable Receive and Transmit */
-       ctl = at91_emac_read(AT91_EMAC_CTL);
-       at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
-}
-
-/*
- * Open the ethernet interface
- */
-static int at91ether_open(struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       unsigned long ctl;
-
-       if (!is_valid_ether_addr(dev->dev_addr))
-               return -EADDRNOTAVAIL;
-
-       clk_enable(lp->ether_clk);              /* Re-enable Peripheral clock */
-
-       /* Clear internal statistics */
-       ctl = at91_emac_read(AT91_EMAC_CTL);
-       at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
-
-       /* Update the MAC address (incase user has changed it) */
-       update_mac_address(dev);
-
-       /* Enable PHY interrupt */
-       enable_phyirq(dev);
-
-       /* Enable MAC interrupts */
-       at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
-                               | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
-                               | AT91_EMAC_ROVR | AT91_EMAC_ABT);
-
-       /* Determine current link speed */
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-       update_linkspeed(dev, 0);
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-
-       at91ether_start(dev);
-       netif_start_queue(dev);
-       return 0;
-}
-
-/*
- * Close the interface
- */
-static int at91ether_close(struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       unsigned long ctl;
-
-       /* Disable Receiver and Transmitter */
-       ctl = at91_emac_read(AT91_EMAC_CTL);
-       at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
-
-       /* Disable PHY interrupt */
-       disable_phyirq(dev);
-
-       /* Disable MAC interrupts */
-       at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
-                               | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
-                               | AT91_EMAC_ROVR | AT91_EMAC_ABT);
-
-       netif_stop_queue(dev);
-
-       clk_disable(lp->ether_clk);             /* Disable Peripheral clock */
-
-       return 0;
-}
-
-/*
- * Transmit packet.
- */
-static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-
-       if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
-               netif_stop_queue(dev);
-
-               /* Store packet information (to free when Tx completed) */
-               lp->skb = skb;
-               lp->skb_length = skb->len;
-               lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
-               dev->stats.tx_bytes += skb->len;
-
-               /* Set address of the data in the Transmit Address register */
-               at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
-               /* Set length of the packet in the Transmit Control register */
-               at91_emac_write(AT91_EMAC_TCR, skb->len);
-
-       } else {
-               printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
-               return NETDEV_TX_BUSY;  /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
-                               on this skb, he also reports -ENETDOWN and printk's, so either
-                               we free and return(0) or don't free and return 1 */
-       }
-
-       return NETDEV_TX_OK;
-}
-
-/*
- * Update the current statistics from the internal statistics registers.
- */
-static struct net_device_stats *at91ether_stats(struct net_device *dev)
-{
-       int ale, lenerr, seqe, lcol, ecol;
-
-       if (netif_running(dev)) {
-               dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK);          /* Good frames received */
-               ale = at91_emac_read(AT91_EMAC_ALE);
-               dev->stats.rx_frame_errors += ale;                              /* Alignment errors */
-               lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
-               dev->stats.rx_length_errors += lenerr;                          /* Excessive Length or Undersize Frame error */
-               seqe = at91_emac_read(AT91_EMAC_SEQE);
-               dev->stats.rx_crc_errors += seqe;                               /* CRC error */
-               dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC);    /* Receive buffer not available */
-               dev->stats.rx_errors += (ale + lenerr + seqe
-                       + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
-
-               dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA);         /* Frames successfully transmitted */
-               dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE);     /* Transmit FIFO underruns */
-               dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE);  /* Carrier Sense errors */
-               dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
-
-               lcol = at91_emac_read(AT91_EMAC_LCOL);
-               ecol = at91_emac_read(AT91_EMAC_ECOL);
-               dev->stats.tx_window_errors += lcol;                    /* Late collisions */
-               dev->stats.tx_aborted_errors += ecol;                   /* 16 collisions */
-
-               dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
-       }
-       return &dev->stats;
-}
-
-/*
- * Extract received frame from buffer descriptors and sent to upper layers.
- * (Called from interrupt context)
- */
-static void at91ether_rx(struct net_device *dev)
-{
-       struct at91_private *lp = netdev_priv(dev);
-       struct recv_desc_bufs *dlist;
-       unsigned char *p_recv;
-       struct sk_buff *skb;
-       unsigned int pktlen;
-
-       dlist = lp->dlist;
-       while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
-               p_recv = dlist->recv_buf[lp->rxBuffIndex];
-               pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff;      /* Length of frame including FCS */
-               skb = dev_alloc_skb(pktlen + 2);
-               if (skb != NULL) {
-                       skb_reserve(skb, 2);
-                       memcpy(skb_put(skb, pktlen), p_recv, pktlen);
-
-                       skb->protocol = eth_type_trans(skb, dev);
-                       dev->stats.rx_bytes += pktlen;
-                       netif_rx(skb);
-               }
-               else {
-                       dev->stats.rx_dropped += 1;
-                       printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
-               }
-
-               if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
-                       dev->stats.multicast++;
-
-               dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE;    /* reset ownership bit */
-               if (lp->rxBuffIndex == MAX_RX_DESCR-1)                          /* wrap after last buffer */
-                       lp->rxBuffIndex = 0;
-               else
-                       lp->rxBuffIndex++;
-       }
-}
-
-/*
- * MAC interrupt handler
- */
-static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
-{
-       struct net_device *dev = (struct net_device *) dev_id;
-       struct at91_private *lp = netdev_priv(dev);
-       unsigned long intstatus, ctl;
-
-       /* MAC Interrupt Status register indicates what interrupts are pending.
-          It is automatically cleared once read. */
-       intstatus = at91_emac_read(AT91_EMAC_ISR);
-
-       if (intstatus & AT91_EMAC_RCOM)         /* Receive complete */
-               at91ether_rx(dev);
-
-       if (intstatus & AT91_EMAC_TCOM) {       /* Transmit complete */
-               /* The TCOM bit is set even if the transmission failed. */
-               if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
-                       dev->stats.tx_errors += 1;
-
-               if (lp->skb) {
-                       dev_kfree_skb_irq(lp->skb);
-                       lp->skb = NULL;
-                       dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
-               }
-               netif_wake_queue(dev);
-       }
-
-       /* Work-around for Errata #11 */
-       if (intstatus & AT91_EMAC_RBNA) {
-               ctl = at91_emac_read(AT91_EMAC_CTL);
-               at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
-               at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
-       }
-
-       if (intstatus & AT91_EMAC_ROVR)
-               printk("%s: ROVR error\n", dev->name);
-
-       return IRQ_HANDLED;
-}
-
-#ifdef CONFIG_NET_POLL_CONTROLLER
-static void at91ether_poll_controller(struct net_device *dev)
-{
-       unsigned long flags;
-
-       local_irq_save(flags);
-       at91ether_interrupt(dev->irq, dev);
-       local_irq_restore(flags);
-}
-#endif
-
-static const struct net_device_ops at91ether_netdev_ops = {
-       .ndo_open               = at91ether_open,
-       .ndo_stop               = at91ether_close,
-       .ndo_start_xmit         = at91ether_start_xmit,
-       .ndo_get_stats          = at91ether_stats,
-       .ndo_set_multicast_list = at91ether_set_multicast_list,
-       .ndo_set_mac_address    = set_mac_address,
-       .ndo_do_ioctl           = at91ether_ioctl,
-       .ndo_validate_addr      = eth_validate_addr,
-       .ndo_change_mtu         = eth_change_mtu,
-#ifdef CONFIG_NET_POLL_CONTROLLER
-       .ndo_poll_controller    = at91ether_poll_controller,
-#endif
-};
-
-/*
- * Initialize the ethernet interface
- */
-static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
-                       struct platform_device *pdev, struct clk *ether_clk)
-{
-       struct at91_eth_data *board_data = pdev->dev.platform_data;
-       struct net_device *dev;
-       struct at91_private *lp;
-       unsigned int val;
-       int res;
-
-       dev = alloc_etherdev(sizeof(struct at91_private));
-       if (!dev)
-               return -ENOMEM;
-
-       dev->base_addr = AT91_VA_BASE_EMAC;
-       dev->irq = AT91RM9200_ID_EMAC;
-
-       /* Install the interrupt handler */
-       if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
-               free_netdev(dev);
-               return -EBUSY;
-       }
-
-       /* Allocate memory for DMA Receive descriptors */
-       lp = netdev_priv(dev);
-       lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
-       if (lp->dlist == NULL) {
-               free_irq(dev->irq, dev);
-               free_netdev(dev);
-               return -ENOMEM;
-       }
-       lp->board_data = *board_data;
-       lp->ether_clk = ether_clk;
-       platform_set_drvdata(pdev, dev);
-
-       spin_lock_init(&lp->lock);
-
-       ether_setup(dev);
-       dev->netdev_ops = &at91ether_netdev_ops;
-       dev->ethtool_ops = &at91ether_ethtool_ops;
-
-       SET_NETDEV_DEV(dev, &pdev->dev);
-
-       get_mac_address(dev);           /* Get ethernet address and store it in dev->dev_addr */
-       update_mac_address(dev);        /* Program ethernet address into MAC */
-
-       at91_emac_write(AT91_EMAC_CTL, 0);
-
-       if (lp->board_data.is_rmii)
-               at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
-       else
-               at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
-
-       /* Perform PHY-specific initialization */
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-       if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
-               read_phy(phy_address, MII_DSCR_REG, &val);
-               if ((val & (1 << 10)) == 0)                     /* DSCR bit 10 is 0 -- fiber mode */
-                       lp->phy_media = PORT_FIBRE;
-       } else if (machine_is_csb337()) {
-               /* mix link activity status into LED2 link state */
-               write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
-       } else if (machine_is_ecbat91())
-               write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
-
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-
-       lp->mii.dev = dev;              /* Support for ethtool */
-       lp->mii.mdio_read = mdio_read;
-       lp->mii.mdio_write = mdio_write;
-       lp->mii.phy_id = phy_address;
-       lp->mii.phy_id_mask = 0x1f;
-       lp->mii.reg_num_mask = 0x1f;
-
-       lp->phy_type = phy_type;        /* Type of PHY connected */
-       lp->phy_address = phy_address;  /* MDI address of PHY */
-
-       /* Register the network interface */
-       res = register_netdev(dev);
-       if (res) {
-               free_irq(dev->irq, dev);
-               free_netdev(dev);
-               dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
-               return res;
-       }
-
-       /* Determine current link speed */
-       spin_lock_irq(&lp->lock);
-       enable_mdi();
-       update_linkspeed(dev, 0);
-       disable_mdi();
-       spin_unlock_irq(&lp->lock);
-       netif_carrier_off(dev);         /* will be enabled in open() */
-
-       /* If board has no PHY IRQ, use a timer to poll the PHY */
-       if (!lp->board_data.phy_irq_pin) {
-               init_timer(&lp->check_timer);
-               lp->check_timer.data = (unsigned long)dev;
-               lp->check_timer.function = at91ether_check_link;
-       } else if (lp->board_data.phy_irq_pin >= 32)
-               gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy");
-
-       /* Display ethernet banner */
-       printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
-              dev->name, (uint) dev->base_addr, dev->irq,
-              at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
-              at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
-              dev->dev_addr);
-       if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
-               printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
-       else if (phy_type == MII_LXT971A_ID)
-               printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
-       else if (phy_type == MII_RTL8201_ID)
-               printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
-       else if (phy_type == MII_BCM5221_ID)
-               printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
-       else if (phy_type == MII_DP83847_ID)
-               printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
-       else if (phy_type == MII_DP83848_ID)
-               printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
-       else if (phy_type == MII_AC101L_ID)
-               printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
-       else if (phy_type == MII_KS8721_ID)
-               printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
-       else if (phy_type == MII_T78Q21x3_ID)
-               printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
-       else if (phy_type == MII_LAN83C185_ID)
-               printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
-
-       return 0;
-}
-
-/*
- * Detect MAC and PHY and perform initialization
- */
-static int __init at91ether_probe(struct platform_device *pdev)
-{
-       unsigned int phyid1, phyid2;
-       int detected = -1;
-       unsigned long phy_id;
-       unsigned short phy_address = 0;
-       struct clk *ether_clk;
-
-       ether_clk = clk_get(&pdev->dev, "ether_clk");
-       if (IS_ERR(ether_clk)) {
-               printk(KERN_ERR "at91_ether: no clock defined\n");
-               return -ENODEV;
-       }
-       clk_enable(ether_clk);                                  /* Enable Peripheral clock */
-
-       while ((detected != 0) && (phy_address < 32)) {
-               /* Read the PHY ID registers */
-               enable_mdi();
-               read_phy(phy_address, MII_PHYSID1, &phyid1);
-               read_phy(phy_address, MII_PHYSID2, &phyid2);
-               disable_mdi();
-
-               phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
-               switch (phy_id) {
-                       case MII_DM9161_ID:             /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
-                       case MII_DM9161A_ID:            /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
-                       case MII_LXT971A_ID:            /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
-                       case MII_RTL8201_ID:            /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
-                       case MII_BCM5221_ID:            /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
-                       case MII_DP83847_ID:            /* National Semiconductor DP83847:  */
-                       case MII_DP83848_ID:            /* National Semiconductor DP83848:  */
-                       case MII_AC101L_ID:             /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
-                       case MII_KS8721_ID:             /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
-                       case MII_T78Q21x3_ID:           /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
-                       case MII_LAN83C185_ID:          /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
-                               detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
-                               break;
-               }
-
-               phy_address++;
-       }
-
-       clk_disable(ether_clk);                                 /* Disable Peripheral clock */
-
-       return detected;
-}
-
-static int __devexit at91ether_remove(struct platform_device *pdev)
-{
-       struct net_device *dev = platform_get_drvdata(pdev);
-       struct at91_private *lp = netdev_priv(dev);
-
-       if (lp->board_data.phy_irq_pin >= 32)
-               gpio_free(lp->board_data.phy_irq_pin);
-
-       unregister_netdev(dev);
-       free_irq(dev->irq, dev);
-       dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
-       clk_put(lp->ether_clk);
-
-       platform_set_drvdata(pdev, NULL);
-       free_netdev(dev);
-       return 0;
-}
-
-#ifdef CONFIG_PM
-
-static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
-{
-       struct net_device *net_dev = platform_get_drvdata(pdev);
-       struct at91_private *lp = netdev_priv(net_dev);
-       int phy_irq = lp->board_data.phy_irq_pin;
-
-       if (netif_running(net_dev)) {
-               if (phy_irq)
-                       disable_irq(phy_irq);
-
-               netif_stop_queue(net_dev);
-               netif_device_detach(net_dev);
-
-               clk_disable(lp->ether_clk);
-       }
-       return 0;
-}
-
-static int at91ether_resume(struct platform_device *pdev)
-{
-       struct net_device *net_dev = platform_get_drvdata(pdev);
-       struct at91_private *lp = netdev_priv(net_dev);
-       int phy_irq = lp->board_data.phy_irq_pin;
-
-       if (netif_running(net_dev)) {
-               clk_enable(lp->ether_clk);
-
-               netif_device_attach(net_dev);
-               netif_start_queue(net_dev);
-
-               if (phy_irq)
-                       enable_irq(phy_irq);
-       }
-       return 0;
-}
-
-#else
-#define at91ether_suspend      NULL
-#define at91ether_resume       NULL
-#endif
-
-static struct platform_driver at91ether_driver = {
-       .remove         = __devexit_p(at91ether_remove),
-       .suspend        = at91ether_suspend,
-       .resume         = at91ether_resume,
-       .driver         = {
-               .name   = DRV_NAME,
-               .owner  = THIS_MODULE,
-       },
-};
-
-static int __init at91ether_init(void)
-{
-       return platform_driver_probe(&at91ether_driver, at91ether_probe);
-}
-
-static void __exit at91ether_exit(void)
-{
-       platform_driver_unregister(&at91ether_driver);
-}
-
-module_init(at91ether_init)
-module_exit(at91ether_exit)
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
-MODULE_AUTHOR("Andrew Victor");
-MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/net/arm/at91_ether.h b/drivers/net/arm/at91_ether.h
deleted file mode 100644 (file)
index 353f4da..0000000
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Ethernet driver for the Atmel AT91RM9200 (Thunder)
- *
- *  Copyright (C) SAN People (Pty) Ltd
- *
- * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
- * Initial version by Rick Bronson.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef AT91_ETHERNET
-#define AT91_ETHERNET
-
-
-/* Davicom 9161 PHY */
-#define MII_DM9161_ID          0x0181b880
-#define MII_DM9161A_ID         0x0181b8a0
-#define MII_DSCR_REG           16
-#define MII_DSCSR_REG          17
-#define MII_DSINTR_REG         21
-
-/* Intel LXT971A PHY */
-#define MII_LXT971A_ID         0x001378E0
-#define MII_ISINTE_REG         18
-#define MII_ISINTS_REG         19
-#define MII_LEDCTRL_REG                20
-
-/* Realtek RTL8201 PHY */
-#define MII_RTL8201_ID         0x00008200
-
-/* Broadcom BCM5221 PHY */
-#define MII_BCM5221_ID         0x004061e0
-#define MII_BCMINTR_REG                26
-
-/* National Semiconductor DP83847 */
-#define MII_DP83847_ID         0x20005c30
-
-/* National Semiconductor DP83848 */
-#define MII_DP83848_ID         0x20005c90
-#define MII_DPPHYSTS_REG       16
-#define MII_DPMICR_REG         17
-#define MII_DPMISR_REG         18
-
-/* Altima AC101L PHY */
-#define MII_AC101L_ID          0x00225520
-
-/* Micrel KS8721 PHY */
-#define MII_KS8721_ID          0x00221610
-
-/* Teridian 78Q2123/78Q2133 */
-#define MII_T78Q21x3_ID                0x000e7230
-#define MII_T78Q21INT_REG      17
-
-/* SMSC LAN83C185 */
-#define MII_LAN83C185_ID       0x0007C0A0
-
-/* ........................................................................ */
-
-#define MAX_RBUFF_SZ   0x600           /* 1518 rounded up */
-#define MAX_RX_DESCR   9               /* max number of receive buffers */
-
-#define EMAC_DESC_DONE 0x00000001      /* bit for if DMA is done */
-#define EMAC_DESC_WRAP 0x00000002      /* bit for wrap */
-
-#define EMAC_BROADCAST 0x80000000      /* broadcast address */
-#define EMAC_MULTICAST 0x40000000      /* multicast address */
-#define EMAC_UNICAST   0x20000000      /* unicast address */
-
-struct rbf_t
-{
-       unsigned int addr;
-       unsigned long size;
-};
-
-struct recv_desc_bufs
-{
-       struct rbf_t descriptors[MAX_RX_DESCR];         /* must be on sizeof (rbf_t) boundary */
-       char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ];      /* must be on long boundary */
-};
-
-struct at91_private
-{
-       struct mii_if_info mii;                 /* ethtool support */
-       struct at91_eth_data board_data;        /* board-specific configuration */
-       struct clk *ether_clk;                  /* clock */
-
-       /* PHY */
-       unsigned long phy_type;                 /* type of PHY (PHY_ID) */
-       spinlock_t lock;                        /* lock for MDI interface */
-       short phy_media;                        /* media interface type */
-       unsigned short phy_address;             /* 5-bit MDI address of PHY (0..31) */
-       struct timer_list check_timer;          /* Poll link status */
-
-       /* Transmit */
-       struct sk_buff *skb;                    /* holds skb until xmit interrupt completes */
-       dma_addr_t skb_physaddr;                /* phys addr from pci_map_single */
-       int skb_length;                         /* saved skb length for pci_unmap_single */
-
-       /* Receive */
-       int rxBuffIndex;                        /* index into receive descriptor list */
-       struct recv_desc_bufs *dlist;           /* descriptor list address */
-       struct recv_desc_bufs *dlist_phys;      /* descriptor list physical address */
-};
-
-#endif
index e087337f92b5c0294121a7e0a57170f85796632b..68a31b9d7acc3f36d1078a6ed30658ae559b19a0 100644 (file)
@@ -15,6 +15,7 @@ source "drivers/net/ethernet/3com/Kconfig"
 source "drivers/net/ethernet/amd/Kconfig"
 source "drivers/net/ethernet/apple/Kconfig"
 source "drivers/net/ethernet/atheros/Kconfig"
+source "drivers/net/ethernet/cadence/Kconfig"
 source "drivers/net/ethernet/adi/Kconfig"
 source "drivers/net/ethernet/broadcom/Kconfig"
 source "drivers/net/ethernet/brocade/Kconfig"
index 826db27564af72cfea30691b594ad23456a86c6e..0e91c4db9117b2622dd45e1cada119c49bcfd67e 100644 (file)
@@ -7,6 +7,7 @@ obj-$(CONFIG_NET_VENDOR_8390) += 8390/
 obj-$(CONFIG_NET_VENDOR_AMD) += amd/
 obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
 obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
+obj-$(CONFIG_NET_ATMEL) += cadence/
 obj-$(CONFIG_NET_BFIN) += adi/
 obj-$(CONFIG_NET_VENDOR_BROADCOM) += broadcom/
 obj-$(CONFIG_NET_VENDOR_BROCADE) += brocade/
diff --git a/drivers/net/ethernet/cadence/Kconfig b/drivers/net/ethernet/cadence/Kconfig
new file mode 100644 (file)
index 0000000..c00e706
--- /dev/null
@@ -0,0 +1,44 @@
+#
+# Atmel device configuration
+#
+
+config HAVE_NET_MACB
+       bool
+
+config NET_ATMEL
+       bool "Atmel devices"
+       depends on HAVE_NET_MACB || (ARM && ARCH_AT91RM9200)
+       ---help---
+         If you have a network (Ethernet) card belonging to this class, say Y.
+         Make sure you know the name of your card. Read the Ethernet-HOWTO,
+         available from <http://www.tldp.org/docs.html#howto>.
+
+         If unsure, say Y.
+
+         Note that the answer to this question doesn't directly affect the
+         kernel: saying N will just cause the configurator to skip all
+         the remaining Atmel network card questions. If you say Y, you will be
+         asked for your specific card in the following questions.
+
+if NET_ATMEL
+
+config ARM_AT91_ETHER
+       tristate "AT91RM9200 Ethernet support"
+       depends on ARM && ARCH_AT91RM9200
+       select MII
+       ---help---
+         If you wish to compile a kernel for the AT91RM9200 and enable
+         ethernet support, then you should always answer Y to this.
+
+config MACB
+       tristate "Atmel MACB support"
+       depends on HAVE_NET_MACB
+       select PHYLIB
+       ---help---
+         The Atmel MACB ethernet interface is found on many AT32 and AT91
+         parts. Say Y to include support for the MACB chip.
+
+         To compile this driver as a module, choose M here: the module
+         will be called macb.
+
+endif # NET_ATMEL
diff --git a/drivers/net/ethernet/cadence/Makefile b/drivers/net/ethernet/cadence/Makefile
new file mode 100644 (file)
index 0000000..9068b83
--- /dev/null
@@ -0,0 +1,6 @@
+#
+# Makefile for the Atmel network device drivers.
+#
+
+obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
+obj-$(CONFIG_MACB) += macb.o
diff --git a/drivers/net/ethernet/cadence/at91_ether.c b/drivers/net/ethernet/cadence/at91_ether.c
new file mode 100644 (file)
index 0000000..29dc435
--- /dev/null
@@ -0,0 +1,1254 @@
+/*
+ * Ethernet driver for the Atmel AT91RM9200 (Thunder)
+ *
+ *  Copyright (C) 2003 SAN People (Pty) Ltd
+ *
+ * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
+ * Initial version by Rick Bronson 01/11/2003
+ *
+ * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
+ *   (Polaroid Corporation)
+ *
+ * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/mii.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+#include <linux/dma-mapping.h>
+#include <linux/ethtool.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/gfp.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/mach-types.h>
+
+#include <mach/at91rm9200_emac.h>
+#include <mach/gpio.h>
+#include <mach/board.h>
+
+#include "at91_ether.h"
+
+#define DRV_NAME       "at91_ether"
+#define DRV_VERSION    "1.0"
+
+#define LINK_POLL_INTERVAL     (HZ)
+
+/* ..................................................................... */
+
+/*
+ * Read from a EMAC register.
+ */
+static inline unsigned long at91_emac_read(unsigned int reg)
+{
+       void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
+
+       return __raw_readl(emac_base + reg);
+}
+
+/*
+ * Write to a EMAC register.
+ */
+static inline void at91_emac_write(unsigned int reg, unsigned long value)
+{
+       void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
+
+       __raw_writel(value, emac_base + reg);
+}
+
+/* ........................... PHY INTERFACE ........................... */
+
+/*
+ * Enable the MDIO bit in MAC control register
+ * When not called from an interrupt-handler, access to the PHY must be
+ *  protected by a spinlock.
+ */
+static void enable_mdi(void)
+{
+       unsigned long ctl;
+
+       ctl = at91_emac_read(AT91_EMAC_CTL);
+       at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE);    /* enable management port */
+}
+
+/*
+ * Disable the MDIO bit in the MAC control register
+ */
+static void disable_mdi(void)
+{
+       unsigned long ctl;
+
+       ctl = at91_emac_read(AT91_EMAC_CTL);
+       at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE);   /* disable management port */
+}
+
+/*
+ * Wait until the PHY operation is complete.
+ */
+static inline void at91_phy_wait(void) {
+       unsigned long timeout = jiffies + 2;
+
+       while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
+               if (time_after(jiffies, timeout)) {
+                       printk("at91_ether: MIO timeout\n");
+                       break;
+               }
+               cpu_relax();
+       }
+}
+
+/*
+ * Write value to the a PHY register
+ * Note: MDI interface is assumed to already have been enabled.
+ */
+static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
+{
+       at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
+               | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
+
+       /* Wait until IDLE bit in Network Status register is cleared */
+       at91_phy_wait();
+}
+
+/*
+ * Read value stored in a PHY register.
+ * Note: MDI interface is assumed to already have been enabled.
+ */
+static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
+{
+       at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
+               | ((phy_addr & 0x1f) << 23) | (address << 18));
+
+       /* Wait until IDLE bit in Network Status register is cleared */
+       at91_phy_wait();
+
+       *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
+}
+
+/* ........................... PHY MANAGEMENT .......................... */
+
+/*
+ * Access the PHY to determine the current link speed and mode, and update the
+ * MAC accordingly.
+ * If no link or auto-negotiation is busy, then no changes are made.
+ */
+static void update_linkspeed(struct net_device *dev, int silent)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       unsigned int bmsr, bmcr, lpa, mac_cfg;
+       unsigned int speed, duplex;
+
+       if (!mii_link_ok(&lp->mii)) {           /* no link */
+               netif_carrier_off(dev);
+               if (!silent)
+                       printk(KERN_INFO "%s: Link down.\n", dev->name);
+               return;
+       }
+
+       /* Link up, or auto-negotiation still in progress */
+       read_phy(lp->phy_address, MII_BMSR, &bmsr);
+       read_phy(lp->phy_address, MII_BMCR, &bmcr);
+       if (bmcr & BMCR_ANENABLE) {                             /* AutoNegotiation is enabled */
+               if (!(bmsr & BMSR_ANEGCOMPLETE))
+                       return;                 /* Do nothing - another interrupt generated when negotiation complete */
+
+               read_phy(lp->phy_address, MII_LPA, &lpa);
+               if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
+               else speed = SPEED_10;
+               if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
+               else duplex = DUPLEX_HALF;
+       } else {
+               speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
+               duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
+       }
+
+       /* Update the MAC */
+       mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
+       if (speed == SPEED_100) {
+               if (duplex == DUPLEX_FULL)              /* 100 Full Duplex */
+                       mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
+               else                                    /* 100 Half Duplex */
+                       mac_cfg |= AT91_EMAC_SPD;
+       } else {
+               if (duplex == DUPLEX_FULL)              /* 10 Full Duplex */
+                       mac_cfg |= AT91_EMAC_FD;
+               else {}                                 /* 10 Half Duplex */
+       }
+       at91_emac_write(AT91_EMAC_CFG, mac_cfg);
+
+       if (!silent)
+               printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
+       netif_carrier_on(dev);
+}
+
+/*
+ * Handle interrupts from the PHY
+ */
+static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
+{
+       struct net_device *dev = (struct net_device *) dev_id;
+       struct at91_private *lp = netdev_priv(dev);
+       unsigned int phy;
+
+       /*
+        * This hander is triggered on both edges, but the PHY chips expect
+        * level-triggering.  We therefore have to check if the PHY actually has
+        * an IRQ pending.
+        */
+       enable_mdi();
+       if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
+               read_phy(lp->phy_address, MII_DSINTR_REG, &phy);        /* ack interrupt in Davicom PHY */
+               if (!(phy & (1 << 0)))
+                       goto done;
+       }
+       else if (lp->phy_type == MII_LXT971A_ID) {
+               read_phy(lp->phy_address, MII_ISINTS_REG, &phy);        /* ack interrupt in Intel PHY */
+               if (!(phy & (1 << 2)))
+                       goto done;
+       }
+       else if (lp->phy_type == MII_BCM5221_ID) {
+               read_phy(lp->phy_address, MII_BCMINTR_REG, &phy);       /* ack interrupt in Broadcom PHY */
+               if (!(phy & (1 << 0)))
+                       goto done;
+       }
+       else if (lp->phy_type == MII_KS8721_ID) {
+               read_phy(lp->phy_address, MII_TPISTATUS, &phy);         /* ack interrupt in Micrel PHY */
+               if (!(phy & ((1 << 2) | 1)))
+                       goto done;
+       }
+       else if (lp->phy_type == MII_T78Q21x3_ID) {                     /* ack interrupt in Teridian PHY */
+               read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
+               if (!(phy & ((1 << 2) | 1)))
+                       goto done;
+       }
+       else if (lp->phy_type == MII_DP83848_ID) {
+               read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy);      /* ack interrupt in DP83848 PHY */
+               if (!(phy & (1 << 7)))
+                       goto done;
+       }
+
+       update_linkspeed(dev, 0);
+
+done:
+       disable_mdi();
+
+       return IRQ_HANDLED;
+}
+
+/*
+ * Initialize and enable the PHY interrupt for link-state changes
+ */
+static void enable_phyirq(struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       unsigned int dsintr, irq_number;
+       int status;
+
+       irq_number = lp->board_data.phy_irq_pin;
+       if (!irq_number) {
+               /*
+                * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
+                * or board does not have it connected.
+                */
+               mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
+               return;
+       }
+
+       status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
+       if (status) {
+               printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
+               return;
+       }
+
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+
+       if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {      /* for Davicom PHY */
+               read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
+               dsintr = dsintr & ~0xf00;               /* clear bits 8..11 */
+               write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
+       }
+       else if (lp->phy_type == MII_LXT971A_ID) {      /* for Intel PHY */
+               read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
+               dsintr = dsintr | 0xf2;                 /* set bits 1, 4..7 */
+               write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
+       }
+       else if (lp->phy_type == MII_BCM5221_ID) {      /* for Broadcom PHY */
+               dsintr = (1 << 15) | ( 1 << 14);
+               write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
+       }
+       else if (lp->phy_type == MII_KS8721_ID) {       /* for Micrel PHY */
+               dsintr = (1 << 10) | ( 1 << 8);
+               write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
+       }
+       else if (lp->phy_type == MII_T78Q21x3_ID) {     /* for Teridian PHY */
+               read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
+               dsintr = dsintr | 0x500;                /* set bits 8, 10 */
+               write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
+       }
+       else if (lp->phy_type == MII_DP83848_ID) {      /* National Semiconductor DP83848 PHY */
+               read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
+               dsintr = dsintr | 0x3c;                 /* set bits 2..5 */
+               write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
+               read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
+               dsintr = dsintr | 0x3;                  /* set bits 0,1 */
+               write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
+       }
+
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+}
+
+/*
+ * Disable the PHY interrupt
+ */
+static void disable_phyirq(struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       unsigned int dsintr;
+       unsigned int irq_number;
+
+       irq_number = lp->board_data.phy_irq_pin;
+       if (!irq_number) {
+               del_timer_sync(&lp->check_timer);
+               return;
+       }
+
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+
+       if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {      /* for Davicom PHY */
+               read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
+               dsintr = dsintr | 0xf00;                        /* set bits 8..11 */
+               write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
+       }
+       else if (lp->phy_type == MII_LXT971A_ID) {      /* for Intel PHY */
+               read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
+               dsintr = dsintr & ~0xf2;                        /* clear bits 1, 4..7 */
+               write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
+       }
+       else if (lp->phy_type == MII_BCM5221_ID) {      /* for Broadcom PHY */
+               read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
+               dsintr = ~(1 << 14);
+               write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
+       }
+       else if (lp->phy_type == MII_KS8721_ID) {       /* for Micrel PHY */
+               read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
+               dsintr = ~((1 << 10) | (1 << 8));
+               write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
+       }
+       else if (lp->phy_type == MII_T78Q21x3_ID) {     /* for Teridian PHY */
+               read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
+               dsintr = dsintr & ~0x500;                       /* clear bits 8, 10 */
+               write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
+       }
+       else if (lp->phy_type == MII_DP83848_ID) {      /* National Semiconductor DP83848 PHY */
+               read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
+               dsintr = dsintr & ~0x3;                         /* clear bits 0, 1 */
+               write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
+               read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
+               dsintr = dsintr & ~0x3c;                        /* clear bits 2..5 */
+               write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
+       }
+
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+
+       free_irq(irq_number, dev);                      /* Free interrupt handler */
+}
+
+/*
+ * Perform a software reset of the PHY.
+ */
+#if 0
+static void reset_phy(struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       unsigned int bmcr;
+
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+
+       /* Perform PHY reset */
+       write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
+
+       /* Wait until PHY reset is complete */
+       do {
+               read_phy(lp->phy_address, MII_BMCR, &bmcr);
+       } while (!(bmcr & BMCR_RESET));
+
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+}
+#endif
+
+static void at91ether_check_link(unsigned long dev_id)
+{
+       struct net_device *dev = (struct net_device *) dev_id;
+       struct at91_private *lp = netdev_priv(dev);
+
+       enable_mdi();
+       update_linkspeed(dev, 1);
+       disable_mdi();
+
+       mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
+}
+
+/* ......................... ADDRESS MANAGEMENT ........................ */
+
+/*
+ * NOTE: Your bootloader must always set the MAC address correctly before
+ * booting into Linux.
+ *
+ * - It must always set the MAC address after reset, even if it doesn't
+ *   happen to access the Ethernet while it's booting.  Some versions of
+ *   U-Boot on the AT91RM9200-DK do not do this.
+ *
+ * - Likewise it must store the addresses in the correct byte order.
+ *   MicroMonitor (uMon) on the CSB337 does this incorrectly (and
+ *   continues to do so, for bug-compatibility).
+ */
+
+static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
+{
+       char addr[6];
+
+       if (machine_is_csb337()) {
+               addr[5] = (lo & 0xff);                  /* The CSB337 bootloader stores the MAC the wrong-way around */
+               addr[4] = (lo & 0xff00) >> 8;
+               addr[3] = (lo & 0xff0000) >> 16;
+               addr[2] = (lo & 0xff000000) >> 24;
+               addr[1] = (hi & 0xff);
+               addr[0] = (hi & 0xff00) >> 8;
+       }
+       else {
+               addr[0] = (lo & 0xff);
+               addr[1] = (lo & 0xff00) >> 8;
+               addr[2] = (lo & 0xff0000) >> 16;
+               addr[3] = (lo & 0xff000000) >> 24;
+               addr[4] = (hi & 0xff);
+               addr[5] = (hi & 0xff00) >> 8;
+       }
+
+       if (is_valid_ether_addr(addr)) {
+               memcpy(dev->dev_addr, &addr, 6);
+               return 1;
+       }
+       return 0;
+}
+
+/*
+ * Set the ethernet MAC address in dev->dev_addr
+ */
+static void __init get_mac_address(struct net_device *dev)
+{
+       /* Check Specific-Address 1 */
+       if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
+               return;
+       /* Check Specific-Address 2 */
+       if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
+               return;
+       /* Check Specific-Address 3 */
+       if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
+               return;
+       /* Check Specific-Address 4 */
+       if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
+               return;
+
+       printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
+}
+
+/*
+ * Program the hardware MAC address from dev->dev_addr.
+ */
+static void update_mac_address(struct net_device *dev)
+{
+       at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
+       at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
+
+       at91_emac_write(AT91_EMAC_SA2L, 0);
+       at91_emac_write(AT91_EMAC_SA2H, 0);
+}
+
+/*
+ * Store the new hardware address in dev->dev_addr, and update the MAC.
+ */
+static int set_mac_address(struct net_device *dev, void* addr)
+{
+       struct sockaddr *address = addr;
+
+       if (!is_valid_ether_addr(address->sa_data))
+               return -EADDRNOTAVAIL;
+
+       memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
+       update_mac_address(dev);
+
+       printk("%s: Setting MAC address to %pM\n", dev->name,
+              dev->dev_addr);
+
+       return 0;
+}
+
+static int inline hash_bit_value(int bitnr, __u8 *addr)
+{
+       if (addr[bitnr / 8] & (1 << (bitnr % 8)))
+               return 1;
+       return 0;
+}
+
+/*
+ * The hash address register is 64 bits long and takes up two locations in the memory map.
+ * The least significant bits are stored in EMAC_HSL and the most significant
+ * bits in EMAC_HSH.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network configuration
+ *  register enable the reception of hash matched frames. The destination address is
+ *  reduced to a 6 bit index into the 64 bit hash register using the following hash function.
+ * The hash function is an exclusive or of every sixth bit of the destination address.
+ *   hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
+ *   hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
+ *   hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
+ *   hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
+ *   hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
+ *   hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
+ * da[0] represents the least significant bit of the first byte received, that is, the multicast/
+ *  unicast indicator, and da[47] represents the most significant bit of the last byte
+ *  received.
+ * If the hash index points to a bit that is set in the hash register then the frame will be
+ *  matched according to whether the frame is multicast or unicast.
+ * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
+ *  the hash index points to a bit set in the hash register.
+ * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
+ *  hash index points to a bit set in the hash register.
+ * To receive all multicast frames, the hash register should be set with all ones and the
+ *  multicast hash enable bit should be set in the network configuration register.
+ */
+
+/*
+ * Return the hash index value for the specified address.
+ */
+static int hash_get_index(__u8 *addr)
+{
+       int i, j, bitval;
+       int hash_index = 0;
+
+       for (j = 0; j < 6; j++) {
+               for (i = 0, bitval = 0; i < 8; i++)
+                       bitval ^= hash_bit_value(i*6 + j, addr);
+
+               hash_index |= (bitval << j);
+       }
+
+       return hash_index;
+}
+
+/*
+ * Add multicast addresses to the internal multicast-hash table.
+ */
+static void at91ether_sethashtable(struct net_device *dev)
+{
+       struct netdev_hw_addr *ha;
+       unsigned long mc_filter[2];
+       unsigned int bitnr;
+
+       mc_filter[0] = mc_filter[1] = 0;
+
+       netdev_for_each_mc_addr(ha, dev) {
+               bitnr = hash_get_index(ha->addr);
+               mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
+       }
+
+       at91_emac_write(AT91_EMAC_HSL, mc_filter[0]);
+       at91_emac_write(AT91_EMAC_HSH, mc_filter[1]);
+}
+
+/*
+ * Enable/Disable promiscuous and multicast modes.
+ */
+static void at91ether_set_multicast_list(struct net_device *dev)
+{
+       unsigned long cfg;
+
+       cfg = at91_emac_read(AT91_EMAC_CFG);
+
+       if (dev->flags & IFF_PROMISC)                   /* Enable promiscuous mode */
+               cfg |= AT91_EMAC_CAF;
+       else if (dev->flags & (~IFF_PROMISC))           /* Disable promiscuous mode */
+               cfg &= ~AT91_EMAC_CAF;
+
+       if (dev->flags & IFF_ALLMULTI) {                /* Enable all multicast mode */
+               at91_emac_write(AT91_EMAC_HSH, -1);
+               at91_emac_write(AT91_EMAC_HSL, -1);
+               cfg |= AT91_EMAC_MTI;
+       } else if (!netdev_mc_empty(dev)) { /* Enable specific multicasts */
+               at91ether_sethashtable(dev);
+               cfg |= AT91_EMAC_MTI;
+       } else if (dev->flags & (~IFF_ALLMULTI)) {      /* Disable all multicast mode */
+               at91_emac_write(AT91_EMAC_HSH, 0);
+               at91_emac_write(AT91_EMAC_HSL, 0);
+               cfg &= ~AT91_EMAC_MTI;
+       }
+
+       at91_emac_write(AT91_EMAC_CFG, cfg);
+}
+
+/* ......................... ETHTOOL SUPPORT ........................... */
+
+static int mdio_read(struct net_device *dev, int phy_id, int location)
+{
+       unsigned int value;
+
+       read_phy(phy_id, location, &value);
+       return value;
+}
+
+static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
+{
+       write_phy(phy_id, location, value);
+}
+
+static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       int ret;
+
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+
+       ret = mii_ethtool_gset(&lp->mii, cmd);
+
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+
+       if (lp->phy_media == PORT_FIBRE) {              /* override media type since mii.c doesn't know */
+               cmd->supported = SUPPORTED_FIBRE;
+               cmd->port = PORT_FIBRE;
+       }
+
+       return ret;
+}
+
+static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       int ret;
+
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+
+       ret = mii_ethtool_sset(&lp->mii, cmd);
+
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+
+       return ret;
+}
+
+static int at91ether_nwayreset(struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       int ret;
+
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+
+       ret = mii_nway_restart(&lp->mii);
+
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+
+       return ret;
+}
+
+static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
+{
+       strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
+       strlcpy(info->version, DRV_VERSION, sizeof(info->version));
+       strlcpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
+}
+
+static const struct ethtool_ops at91ether_ethtool_ops = {
+       .get_settings   = at91ether_get_settings,
+       .set_settings   = at91ether_set_settings,
+       .get_drvinfo    = at91ether_get_drvinfo,
+       .nway_reset     = at91ether_nwayreset,
+       .get_link       = ethtool_op_get_link,
+};
+
+static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       int res;
+
+       if (!netif_running(dev))
+               return -EINVAL;
+
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+       res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+
+       return res;
+}
+
+/* ................................ MAC ................................ */
+
+/*
+ * Initialize and start the Receiver and Transmit subsystems
+ */
+static void at91ether_start(struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       struct recv_desc_bufs *dlist, *dlist_phys;
+       int i;
+       unsigned long ctl;
+
+       dlist = lp->dlist;
+       dlist_phys = lp->dlist_phys;
+
+       for (i = 0; i < MAX_RX_DESCR; i++) {
+               dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
+               dlist->descriptors[i].size = 0;
+       }
+
+       /* Set the Wrap bit on the last descriptor */
+       dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
+
+       /* Reset buffer index */
+       lp->rxBuffIndex = 0;
+
+       /* Program address of descriptor list in Rx Buffer Queue register */
+       at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
+
+       /* Enable Receive and Transmit */
+       ctl = at91_emac_read(AT91_EMAC_CTL);
+       at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
+}
+
+/*
+ * Open the ethernet interface
+ */
+static int at91ether_open(struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       unsigned long ctl;
+
+       if (!is_valid_ether_addr(dev->dev_addr))
+               return -EADDRNOTAVAIL;
+
+       clk_enable(lp->ether_clk);              /* Re-enable Peripheral clock */
+
+       /* Clear internal statistics */
+       ctl = at91_emac_read(AT91_EMAC_CTL);
+       at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
+
+       /* Update the MAC address (incase user has changed it) */
+       update_mac_address(dev);
+
+       /* Enable PHY interrupt */
+       enable_phyirq(dev);
+
+       /* Enable MAC interrupts */
+       at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
+                               | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
+                               | AT91_EMAC_ROVR | AT91_EMAC_ABT);
+
+       /* Determine current link speed */
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+       update_linkspeed(dev, 0);
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+
+       at91ether_start(dev);
+       netif_start_queue(dev);
+       return 0;
+}
+
+/*
+ * Close the interface
+ */
+static int at91ether_close(struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       unsigned long ctl;
+
+       /* Disable Receiver and Transmitter */
+       ctl = at91_emac_read(AT91_EMAC_CTL);
+       at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
+
+       /* Disable PHY interrupt */
+       disable_phyirq(dev);
+
+       /* Disable MAC interrupts */
+       at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
+                               | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
+                               | AT91_EMAC_ROVR | AT91_EMAC_ABT);
+
+       netif_stop_queue(dev);
+
+       clk_disable(lp->ether_clk);             /* Disable Peripheral clock */
+
+       return 0;
+}
+
+/*
+ * Transmit packet.
+ */
+static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+
+       if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
+               netif_stop_queue(dev);
+
+               /* Store packet information (to free when Tx completed) */
+               lp->skb = skb;
+               lp->skb_length = skb->len;
+               lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
+               dev->stats.tx_bytes += skb->len;
+
+               /* Set address of the data in the Transmit Address register */
+               at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
+               /* Set length of the packet in the Transmit Control register */
+               at91_emac_write(AT91_EMAC_TCR, skb->len);
+
+       } else {
+               printk(KERN_ERR "at91_ether.c: at91ether_start_xmit() called, but device is busy!\n");
+               return NETDEV_TX_BUSY;  /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
+                               on this skb, he also reports -ENETDOWN and printk's, so either
+                               we free and return(0) or don't free and return 1 */
+       }
+
+       return NETDEV_TX_OK;
+}
+
+/*
+ * Update the current statistics from the internal statistics registers.
+ */
+static struct net_device_stats *at91ether_stats(struct net_device *dev)
+{
+       int ale, lenerr, seqe, lcol, ecol;
+
+       if (netif_running(dev)) {
+               dev->stats.rx_packets += at91_emac_read(AT91_EMAC_OK);          /* Good frames received */
+               ale = at91_emac_read(AT91_EMAC_ALE);
+               dev->stats.rx_frame_errors += ale;                              /* Alignment errors */
+               lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
+               dev->stats.rx_length_errors += lenerr;                          /* Excessive Length or Undersize Frame error */
+               seqe = at91_emac_read(AT91_EMAC_SEQE);
+               dev->stats.rx_crc_errors += seqe;                               /* CRC error */
+               dev->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC);    /* Receive buffer not available */
+               dev->stats.rx_errors += (ale + lenerr + seqe
+                       + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
+
+               dev->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA);         /* Frames successfully transmitted */
+               dev->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE);     /* Transmit FIFO underruns */
+               dev->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE);  /* Carrier Sense errors */
+               dev->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
+
+               lcol = at91_emac_read(AT91_EMAC_LCOL);
+               ecol = at91_emac_read(AT91_EMAC_ECOL);
+               dev->stats.tx_window_errors += lcol;                    /* Late collisions */
+               dev->stats.tx_aborted_errors += ecol;                   /* 16 collisions */
+
+               dev->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
+       }
+       return &dev->stats;
+}
+
+/*
+ * Extract received frame from buffer descriptors and sent to upper layers.
+ * (Called from interrupt context)
+ */
+static void at91ether_rx(struct net_device *dev)
+{
+       struct at91_private *lp = netdev_priv(dev);
+       struct recv_desc_bufs *dlist;
+       unsigned char *p_recv;
+       struct sk_buff *skb;
+       unsigned int pktlen;
+
+       dlist = lp->dlist;
+       while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
+               p_recv = dlist->recv_buf[lp->rxBuffIndex];
+               pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff;      /* Length of frame including FCS */
+               skb = dev_alloc_skb(pktlen + 2);
+               if (skb != NULL) {
+                       skb_reserve(skb, 2);
+                       memcpy(skb_put(skb, pktlen), p_recv, pktlen);
+
+                       skb->protocol = eth_type_trans(skb, dev);
+                       dev->stats.rx_bytes += pktlen;
+                       netif_rx(skb);
+               }
+               else {
+                       dev->stats.rx_dropped += 1;
+                       printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
+               }
+
+               if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
+                       dev->stats.multicast++;
+
+               dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE;    /* reset ownership bit */
+               if (lp->rxBuffIndex == MAX_RX_DESCR-1)                          /* wrap after last buffer */
+                       lp->rxBuffIndex = 0;
+               else
+                       lp->rxBuffIndex++;
+       }
+}
+
+/*
+ * MAC interrupt handler
+ */
+static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
+{
+       struct net_device *dev = (struct net_device *) dev_id;
+       struct at91_private *lp = netdev_priv(dev);
+       unsigned long intstatus, ctl;
+
+       /* MAC Interrupt Status register indicates what interrupts are pending.
+          It is automatically cleared once read. */
+       intstatus = at91_emac_read(AT91_EMAC_ISR);
+
+       if (intstatus & AT91_EMAC_RCOM)         /* Receive complete */
+               at91ether_rx(dev);
+
+       if (intstatus & AT91_EMAC_TCOM) {       /* Transmit complete */
+               /* The TCOM bit is set even if the transmission failed. */
+               if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
+                       dev->stats.tx_errors += 1;
+
+               if (lp->skb) {
+                       dev_kfree_skb_irq(lp->skb);
+                       lp->skb = NULL;
+                       dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
+               }
+               netif_wake_queue(dev);
+       }
+
+       /* Work-around for Errata #11 */
+       if (intstatus & AT91_EMAC_RBNA) {
+               ctl = at91_emac_read(AT91_EMAC_CTL);
+               at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
+               at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
+       }
+
+       if (intstatus & AT91_EMAC_ROVR)
+               printk("%s: ROVR error\n", dev->name);
+
+       return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+static void at91ether_poll_controller(struct net_device *dev)
+{
+       unsigned long flags;
+
+       local_irq_save(flags);
+       at91ether_interrupt(dev->irq, dev);
+       local_irq_restore(flags);
+}
+#endif
+
+static const struct net_device_ops at91ether_netdev_ops = {
+       .ndo_open               = at91ether_open,
+       .ndo_stop               = at91ether_close,
+       .ndo_start_xmit         = at91ether_start_xmit,
+       .ndo_get_stats          = at91ether_stats,
+       .ndo_set_multicast_list = at91ether_set_multicast_list,
+       .ndo_set_mac_address    = set_mac_address,
+       .ndo_do_ioctl           = at91ether_ioctl,
+       .ndo_validate_addr      = eth_validate_addr,
+       .ndo_change_mtu         = eth_change_mtu,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+       .ndo_poll_controller    = at91ether_poll_controller,
+#endif
+};
+
+/*
+ * Initialize the ethernet interface
+ */
+static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
+                       struct platform_device *pdev, struct clk *ether_clk)
+{
+       struct at91_eth_data *board_data = pdev->dev.platform_data;
+       struct net_device *dev;
+       struct at91_private *lp;
+       unsigned int val;
+       int res;
+
+       dev = alloc_etherdev(sizeof(struct at91_private));
+       if (!dev)
+               return -ENOMEM;
+
+       dev->base_addr = AT91_VA_BASE_EMAC;
+       dev->irq = AT91RM9200_ID_EMAC;
+
+       /* Install the interrupt handler */
+       if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
+               free_netdev(dev);
+               return -EBUSY;
+       }
+
+       /* Allocate memory for DMA Receive descriptors */
+       lp = netdev_priv(dev);
+       lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
+       if (lp->dlist == NULL) {
+               free_irq(dev->irq, dev);
+               free_netdev(dev);
+               return -ENOMEM;
+       }
+       lp->board_data = *board_data;
+       lp->ether_clk = ether_clk;
+       platform_set_drvdata(pdev, dev);
+
+       spin_lock_init(&lp->lock);
+
+       ether_setup(dev);
+       dev->netdev_ops = &at91ether_netdev_ops;
+       dev->ethtool_ops = &at91ether_ethtool_ops;
+
+       SET_NETDEV_DEV(dev, &pdev->dev);
+
+       get_mac_address(dev);           /* Get ethernet address and store it in dev->dev_addr */
+       update_mac_address(dev);        /* Program ethernet address into MAC */
+
+       at91_emac_write(AT91_EMAC_CTL, 0);
+
+       if (lp->board_data.is_rmii)
+               at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
+       else
+               at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
+
+       /* Perform PHY-specific initialization */
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+       if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
+               read_phy(phy_address, MII_DSCR_REG, &val);
+               if ((val & (1 << 10)) == 0)                     /* DSCR bit 10 is 0 -- fiber mode */
+                       lp->phy_media = PORT_FIBRE;
+       } else if (machine_is_csb337()) {
+               /* mix link activity status into LED2 link state */
+               write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
+       } else if (machine_is_ecbat91())
+               write_phy(phy_address, MII_LEDCTRL_REG, 0x156A);
+
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+
+       lp->mii.dev = dev;              /* Support for ethtool */
+       lp->mii.mdio_read = mdio_read;
+       lp->mii.mdio_write = mdio_write;
+       lp->mii.phy_id = phy_address;
+       lp->mii.phy_id_mask = 0x1f;
+       lp->mii.reg_num_mask = 0x1f;
+
+       lp->phy_type = phy_type;        /* Type of PHY connected */
+       lp->phy_address = phy_address;  /* MDI address of PHY */
+
+       /* Register the network interface */
+       res = register_netdev(dev);
+       if (res) {
+               free_irq(dev->irq, dev);
+               free_netdev(dev);
+               dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
+               return res;
+       }
+
+       /* Determine current link speed */
+       spin_lock_irq(&lp->lock);
+       enable_mdi();
+       update_linkspeed(dev, 0);
+       disable_mdi();
+       spin_unlock_irq(&lp->lock);
+       netif_carrier_off(dev);         /* will be enabled in open() */
+
+       /* If board has no PHY IRQ, use a timer to poll the PHY */
+       if (!lp->board_data.phy_irq_pin) {
+               init_timer(&lp->check_timer);
+               lp->check_timer.data = (unsigned long)dev;
+               lp->check_timer.function = at91ether_check_link;
+       } else if (lp->board_data.phy_irq_pin >= 32)
+               gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy");
+
+       /* Display ethernet banner */
+       printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%pM)\n",
+              dev->name, (uint) dev->base_addr, dev->irq,
+              at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
+              at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
+              dev->dev_addr);
+       if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
+               printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
+       else if (phy_type == MII_LXT971A_ID)
+               printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
+       else if (phy_type == MII_RTL8201_ID)
+               printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
+       else if (phy_type == MII_BCM5221_ID)
+               printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
+       else if (phy_type == MII_DP83847_ID)
+               printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
+       else if (phy_type == MII_DP83848_ID)
+               printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
+       else if (phy_type == MII_AC101L_ID)
+               printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
+       else if (phy_type == MII_KS8721_ID)
+               printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
+       else if (phy_type == MII_T78Q21x3_ID)
+               printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
+       else if (phy_type == MII_LAN83C185_ID)
+               printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
+
+       return 0;
+}
+
+/*
+ * Detect MAC and PHY and perform initialization
+ */
+static int __init at91ether_probe(struct platform_device *pdev)
+{
+       unsigned int phyid1, phyid2;
+       int detected = -1;
+       unsigned long phy_id;
+       unsigned short phy_address = 0;
+       struct clk *ether_clk;
+
+       ether_clk = clk_get(&pdev->dev, "ether_clk");
+       if (IS_ERR(ether_clk)) {
+               printk(KERN_ERR "at91_ether: no clock defined\n");
+               return -ENODEV;
+       }
+       clk_enable(ether_clk);                                  /* Enable Peripheral clock */
+
+       while ((detected != 0) && (phy_address < 32)) {
+               /* Read the PHY ID registers */
+               enable_mdi();
+               read_phy(phy_address, MII_PHYSID1, &phyid1);
+               read_phy(phy_address, MII_PHYSID2, &phyid2);
+               disable_mdi();
+
+               phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
+               switch (phy_id) {
+                       case MII_DM9161_ID:             /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
+                       case MII_DM9161A_ID:            /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
+                       case MII_LXT971A_ID:            /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
+                       case MII_RTL8201_ID:            /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
+                       case MII_BCM5221_ID:            /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
+                       case MII_DP83847_ID:            /* National Semiconductor DP83847:  */
+                       case MII_DP83848_ID:            /* National Semiconductor DP83848:  */
+                       case MII_AC101L_ID:             /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
+                       case MII_KS8721_ID:             /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
+                       case MII_T78Q21x3_ID:           /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
+                       case MII_LAN83C185_ID:          /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
+                               detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
+                               break;
+               }
+
+               phy_address++;
+       }
+
+       clk_disable(ether_clk);                                 /* Disable Peripheral clock */
+
+       return detected;
+}
+
+static int __devexit at91ether_remove(struct platform_device *pdev)
+{
+       struct net_device *dev = platform_get_drvdata(pdev);
+       struct at91_private *lp = netdev_priv(dev);
+
+       if (lp->board_data.phy_irq_pin >= 32)
+               gpio_free(lp->board_data.phy_irq_pin);
+
+       unregister_netdev(dev);
+       free_irq(dev->irq, dev);
+       dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
+       clk_put(lp->ether_clk);
+
+       platform_set_drvdata(pdev, NULL);
+       free_netdev(dev);
+       return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
+{
+       struct net_device *net_dev = platform_get_drvdata(pdev);
+       struct at91_private *lp = netdev_priv(net_dev);
+       int phy_irq = lp->board_data.phy_irq_pin;
+
+       if (netif_running(net_dev)) {
+               if (phy_irq)
+                       disable_irq(phy_irq);
+
+               netif_stop_queue(net_dev);
+               netif_device_detach(net_dev);
+
+               clk_disable(lp->ether_clk);
+       }
+       return 0;
+}
+
+static int at91ether_resume(struct platform_device *pdev)
+{
+       struct net_device *net_dev = platform_get_drvdata(pdev);
+       struct at91_private *lp = netdev_priv(net_dev);
+       int phy_irq = lp->board_data.phy_irq_pin;
+
+       if (netif_running(net_dev)) {
+               clk_enable(lp->ether_clk);
+
+               netif_device_attach(net_dev);
+               netif_start_queue(net_dev);
+
+               if (phy_irq)
+                       enable_irq(phy_irq);
+       }
+       return 0;
+}
+
+#else
+#define at91ether_suspend      NULL
+#define at91ether_resume       NULL
+#endif
+
+static struct platform_driver at91ether_driver = {
+       .remove         = __devexit_p(at91ether_remove),
+       .suspend        = at91ether_suspend,
+       .resume         = at91ether_resume,
+       .driver         = {
+               .name   = DRV_NAME,
+               .owner  = THIS_MODULE,
+       },
+};
+
+static int __init at91ether_init(void)
+{
+       return platform_driver_probe(&at91ether_driver, at91ether_probe);
+}
+
+static void __exit at91ether_exit(void)
+{
+       platform_driver_unregister(&at91ether_driver);
+}
+
+module_init(at91ether_init)
+module_exit(at91ether_exit)
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
+MODULE_AUTHOR("Andrew Victor");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/net/ethernet/cadence/at91_ether.h b/drivers/net/ethernet/cadence/at91_ether.h
new file mode 100644 (file)
index 0000000..353f4da
--- /dev/null
@@ -0,0 +1,109 @@
+/*
+ * Ethernet driver for the Atmel AT91RM9200 (Thunder)
+ *
+ *  Copyright (C) SAN People (Pty) Ltd
+ *
+ * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
+ * Initial version by Rick Bronson.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef AT91_ETHERNET
+#define AT91_ETHERNET
+
+
+/* Davicom 9161 PHY */
+#define MII_DM9161_ID          0x0181b880
+#define MII_DM9161A_ID         0x0181b8a0
+#define MII_DSCR_REG           16
+#define MII_DSCSR_REG          17
+#define MII_DSINTR_REG         21
+
+/* Intel LXT971A PHY */
+#define MII_LXT971A_ID         0x001378E0
+#define MII_ISINTE_REG         18
+#define MII_ISINTS_REG         19
+#define MII_LEDCTRL_REG                20
+
+/* Realtek RTL8201 PHY */
+#define MII_RTL8201_ID         0x00008200
+
+/* Broadcom BCM5221 PHY */
+#define MII_BCM5221_ID         0x004061e0
+#define MII_BCMINTR_REG                26
+
+/* National Semiconductor DP83847 */
+#define MII_DP83847_ID         0x20005c30
+
+/* National Semiconductor DP83848 */
+#define MII_DP83848_ID         0x20005c90
+#define MII_DPPHYSTS_REG       16
+#define MII_DPMICR_REG         17
+#define MII_DPMISR_REG         18
+
+/* Altima AC101L PHY */
+#define MII_AC101L_ID          0x00225520
+
+/* Micrel KS8721 PHY */
+#define MII_KS8721_ID          0x00221610
+
+/* Teridian 78Q2123/78Q2133 */
+#define MII_T78Q21x3_ID                0x000e7230
+#define MII_T78Q21INT_REG      17
+
+/* SMSC LAN83C185 */
+#define MII_LAN83C185_ID       0x0007C0A0
+
+/* ........................................................................ */
+
+#define MAX_RBUFF_SZ   0x600           /* 1518 rounded up */
+#define MAX_RX_DESCR   9               /* max number of receive buffers */
+
+#define EMAC_DESC_DONE 0x00000001      /* bit for if DMA is done */
+#define EMAC_DESC_WRAP 0x00000002      /* bit for wrap */
+
+#define EMAC_BROADCAST 0x80000000      /* broadcast address */
+#define EMAC_MULTICAST 0x40000000      /* multicast address */
+#define EMAC_UNICAST   0x20000000      /* unicast address */
+
+struct rbf_t
+{
+       unsigned int addr;
+       unsigned long size;
+};
+
+struct recv_desc_bufs
+{
+       struct rbf_t descriptors[MAX_RX_DESCR];         /* must be on sizeof (rbf_t) boundary */
+       char recv_buf[MAX_RX_DESCR][MAX_RBUFF_SZ];      /* must be on long boundary */
+};
+
+struct at91_private
+{
+       struct mii_if_info mii;                 /* ethtool support */
+       struct at91_eth_data board_data;        /* board-specific configuration */
+       struct clk *ether_clk;                  /* clock */
+
+       /* PHY */
+       unsigned long phy_type;                 /* type of PHY (PHY_ID) */
+       spinlock_t lock;                        /* lock for MDI interface */
+       short phy_media;                        /* media interface type */
+       unsigned short phy_address;             /* 5-bit MDI address of PHY (0..31) */
+       struct timer_list check_timer;          /* Poll link status */
+
+       /* Transmit */
+       struct sk_buff *skb;                    /* holds skb until xmit interrupt completes */
+       dma_addr_t skb_physaddr;                /* phys addr from pci_map_single */
+       int skb_length;                         /* saved skb length for pci_unmap_single */
+
+       /* Receive */
+       int rxBuffIndex;                        /* index into receive descriptor list */
+       struct recv_desc_bufs *dlist;           /* descriptor list address */
+       struct recv_desc_bufs *dlist_phys;      /* descriptor list physical address */
+};
+
+#endif
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
new file mode 100644 (file)
index 0000000..dc4e305
--- /dev/null
@@ -0,0 +1,1366 @@
+/*
+ * Atmel MACB Ethernet Controller driver
+ *
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/phy.h>
+
+#include <mach/board.h>
+#include <mach/cpu.h>
+
+#include "macb.h"
+
+#define RX_BUFFER_SIZE         128
+#define RX_RING_SIZE           512
+#define RX_RING_BYTES          (sizeof(struct dma_desc) * RX_RING_SIZE)
+
+/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
+#define RX_OFFSET              2
+
+#define TX_RING_SIZE           128
+#define DEF_TX_RING_PENDING    (TX_RING_SIZE - 1)
+#define TX_RING_BYTES          (sizeof(struct dma_desc) * TX_RING_SIZE)
+
+#define TX_RING_GAP(bp)                                                \
+       (TX_RING_SIZE - (bp)->tx_pending)
+#define TX_BUFFS_AVAIL(bp)                                     \
+       (((bp)->tx_tail <= (bp)->tx_head) ?                     \
+        (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head :     \
+        (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
+#define NEXT_TX(n)             (((n) + 1) & (TX_RING_SIZE - 1))
+
+#define NEXT_RX(n)             (((n) + 1) & (RX_RING_SIZE - 1))
+
+/* minimum number of free TX descriptors before waking up TX process */
+#define MACB_TX_WAKEUP_THRESH  (TX_RING_SIZE / 4)
+
+#define MACB_RX_INT_FLAGS      (MACB_BIT(RCOMP) | MACB_BIT(RXUBR)      \
+                                | MACB_BIT(ISR_ROVR))
+
+static void __macb_set_hwaddr(struct macb *bp)
+{
+       u32 bottom;
+       u16 top;
+
+       bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
+       macb_writel(bp, SA1B, bottom);
+       top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
+       macb_writel(bp, SA1T, top);
+}
+
+static void __init macb_get_hwaddr(struct macb *bp)
+{
+       u32 bottom;
+       u16 top;
+       u8 addr[6];
+
+       bottom = macb_readl(bp, SA1B);
+       top = macb_readl(bp, SA1T);
+
+       addr[0] = bottom & 0xff;
+       addr[1] = (bottom >> 8) & 0xff;
+       addr[2] = (bottom >> 16) & 0xff;
+       addr[3] = (bottom >> 24) & 0xff;
+       addr[4] = top & 0xff;
+       addr[5] = (top >> 8) & 0xff;
+
+       if (is_valid_ether_addr(addr)) {
+               memcpy(bp->dev->dev_addr, addr, sizeof(addr));
+       } else {
+               dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
+               random_ether_addr(bp->dev->dev_addr);
+       }
+}
+
+static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+       struct macb *bp = bus->priv;
+       int value;
+
+       macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
+                             | MACB_BF(RW, MACB_MAN_READ)
+                             | MACB_BF(PHYA, mii_id)
+                             | MACB_BF(REGA, regnum)
+                             | MACB_BF(CODE, MACB_MAN_CODE)));
+
+       /* wait for end of transfer */
+       while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
+               cpu_relax();
+
+       value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
+
+       return value;
+}
+
+static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+                          u16 value)
+{
+       struct macb *bp = bus->priv;
+
+       macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
+                             | MACB_BF(RW, MACB_MAN_WRITE)
+                             | MACB_BF(PHYA, mii_id)
+                             | MACB_BF(REGA, regnum)
+                             | MACB_BF(CODE, MACB_MAN_CODE)
+                             | MACB_BF(DATA, value)));
+
+       /* wait for end of transfer */
+       while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
+               cpu_relax();
+
+       return 0;
+}
+
+static int macb_mdio_reset(struct mii_bus *bus)
+{
+       return 0;
+}
+
+static void macb_handle_link_change(struct net_device *dev)
+{
+       struct macb *bp = netdev_priv(dev);
+       struct phy_device *phydev = bp->phy_dev;
+       unsigned long flags;
+
+       int status_change = 0;
+
+       spin_lock_irqsave(&bp->lock, flags);
+
+       if (phydev->link) {
+               if ((bp->speed != phydev->speed) ||
+                   (bp->duplex != phydev->duplex)) {
+                       u32 reg;
+
+                       reg = macb_readl(bp, NCFGR);
+                       reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
+
+                       if (phydev->duplex)
+                               reg |= MACB_BIT(FD);
+                       if (phydev->speed == SPEED_100)
+                               reg |= MACB_BIT(SPD);
+
+                       macb_writel(bp, NCFGR, reg);
+
+                       bp->speed = phydev->speed;
+                       bp->duplex = phydev->duplex;
+                       status_change = 1;
+               }
+       }
+
+       if (phydev->link != bp->link) {
+               if (!phydev->link) {
+                       bp->speed = 0;
+                       bp->duplex = -1;
+               }
+               bp->link = phydev->link;
+
+               status_change = 1;
+       }
+
+       spin_unlock_irqrestore(&bp->lock, flags);
+
+       if (status_change) {
+               if (phydev->link)
+                       printk(KERN_INFO "%s: link up (%d/%s)\n",
+                              dev->name, phydev->speed,
+                              DUPLEX_FULL == phydev->duplex ? "Full":"Half");
+               else
+                       printk(KERN_INFO "%s: link down\n", dev->name);
+       }
+}
+
+/* based on au1000_eth. c*/
+static int macb_mii_probe(struct net_device *dev)
+{
+       struct macb *bp = netdev_priv(dev);
+       struct phy_device *phydev;
+       struct eth_platform_data *pdata;
+       int ret;
+
+       phydev = phy_find_first(bp->mii_bus);
+       if (!phydev) {
+               printk (KERN_ERR "%s: no PHY found\n", dev->name);
+               return -1;
+       }
+
+       pdata = bp->pdev->dev.platform_data;
+       /* TODO : add pin_irq */
+
+       /* attach the mac to the phy */
+       ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
+                                pdata && pdata->is_rmii ?
+                                PHY_INTERFACE_MODE_RMII :
+                                PHY_INTERFACE_MODE_MII);
+       if (ret) {
+               printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+               return ret;
+       }
+
+       /* mask with MAC supported features */
+       phydev->supported &= PHY_BASIC_FEATURES;
+
+       phydev->advertising = phydev->supported;
+
+       bp->link = 0;
+       bp->speed = 0;
+       bp->duplex = -1;
+       bp->phy_dev = phydev;
+
+       return 0;
+}
+
+static int macb_mii_init(struct macb *bp)
+{
+       struct eth_platform_data *pdata;
+       int err = -ENXIO, i;
+
+       /* Enable management port */
+       macb_writel(bp, NCR, MACB_BIT(MPE));
+
+       bp->mii_bus = mdiobus_alloc();
+       if (bp->mii_bus == NULL) {
+               err = -ENOMEM;
+               goto err_out;
+       }
+
+       bp->mii_bus->name = "MACB_mii_bus";
+       bp->mii_bus->read = &macb_mdio_read;
+       bp->mii_bus->write = &macb_mdio_write;
+       bp->mii_bus->reset = &macb_mdio_reset;
+       snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
+       bp->mii_bus->priv = bp;
+       bp->mii_bus->parent = &bp->dev->dev;
+       pdata = bp->pdev->dev.platform_data;
+
+       if (pdata)
+               bp->mii_bus->phy_mask = pdata->phy_mask;
+
+       bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
+       if (!bp->mii_bus->irq) {
+               err = -ENOMEM;
+               goto err_out_free_mdiobus;
+       }
+
+       for (i = 0; i < PHY_MAX_ADDR; i++)
+               bp->mii_bus->irq[i] = PHY_POLL;
+
+       dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
+
+       if (mdiobus_register(bp->mii_bus))
+               goto err_out_free_mdio_irq;
+
+       if (macb_mii_probe(bp->dev) != 0) {
+               goto err_out_unregister_bus;
+       }
+
+       return 0;
+
+err_out_unregister_bus:
+       mdiobus_unregister(bp->mii_bus);
+err_out_free_mdio_irq:
+       kfree(bp->mii_bus->irq);
+err_out_free_mdiobus:
+       mdiobus_free(bp->mii_bus);
+err_out:
+       return err;
+}
+
+static void macb_update_stats(struct macb *bp)
+{
+       u32 __iomem *reg = bp->regs + MACB_PFR;
+       u32 *p = &bp->hw_stats.rx_pause_frames;
+       u32 *end = &bp->hw_stats.tx_pause_frames + 1;
+
+       WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
+
+       for(; p < end; p++, reg++)
+               *p += __raw_readl(reg);
+}
+
+static void macb_tx(struct macb *bp)
+{
+       unsigned int tail;
+       unsigned int head;
+       u32 status;
+
+       status = macb_readl(bp, TSR);
+       macb_writel(bp, TSR, status);
+
+       dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
+               (unsigned long)status);
+
+       if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
+               int i;
+               printk(KERN_ERR "%s: TX %s, resetting buffers\n",
+                       bp->dev->name, status & MACB_BIT(UND) ?
+                       "underrun" : "retry limit exceeded");
+
+               /* Transfer ongoing, disable transmitter, to avoid confusion */
+               if (status & MACB_BIT(TGO))
+                       macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
+
+               head = bp->tx_head;
+
+               /*Mark all the buffer as used to avoid sending a lost buffer*/
+               for (i = 0; i < TX_RING_SIZE; i++)
+                       bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
+
+               /* Add wrap bit */
+               bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
+
+               /* free transmit buffer in upper layer*/
+               for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
+                       struct ring_info *rp = &bp->tx_skb[tail];
+                       struct sk_buff *skb = rp->skb;
+
+                       BUG_ON(skb == NULL);
+
+                       rmb();
+
+                       dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
+                                                        DMA_TO_DEVICE);
+                       rp->skb = NULL;
+                       dev_kfree_skb_irq(skb);
+               }
+
+               bp->tx_head = bp->tx_tail = 0;
+
+               /* Enable the transmitter again */
+               if (status & MACB_BIT(TGO))
+                       macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
+       }
+
+       if (!(status & MACB_BIT(COMP)))
+               /*
+                * This may happen when a buffer becomes complete
+                * between reading the ISR and scanning the
+                * descriptors.  Nothing to worry about.
+                */
+               return;
+
+       head = bp->tx_head;
+       for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
+               struct ring_info *rp = &bp->tx_skb[tail];
+               struct sk_buff *skb = rp->skb;
+               u32 bufstat;
+
+               BUG_ON(skb == NULL);
+
+               rmb();
+               bufstat = bp->tx_ring[tail].ctrl;
+
+               if (!(bufstat & MACB_BIT(TX_USED)))
+                       break;
+
+               dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
+                       tail, skb->data);
+               dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
+                                DMA_TO_DEVICE);
+               bp->stats.tx_packets++;
+               bp->stats.tx_bytes += skb->len;
+               rp->skb = NULL;
+               dev_kfree_skb_irq(skb);
+       }
+
+       bp->tx_tail = tail;
+       if (netif_queue_stopped(bp->dev) &&
+           TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
+               netif_wake_queue(bp->dev);
+}
+
+static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
+                        unsigned int last_frag)
+{
+       unsigned int len;
+       unsigned int frag;
+       unsigned int offset = 0;
+       struct sk_buff *skb;
+
+       len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
+
+       dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
+               first_frag, last_frag, len);
+
+       skb = dev_alloc_skb(len + RX_OFFSET);
+       if (!skb) {
+               bp->stats.rx_dropped++;
+               for (frag = first_frag; ; frag = NEXT_RX(frag)) {
+                       bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
+                       if (frag == last_frag)
+                               break;
+               }
+               wmb();
+               return 1;
+       }
+
+       skb_reserve(skb, RX_OFFSET);
+       skb_checksum_none_assert(skb);
+       skb_put(skb, len);
+
+       for (frag = first_frag; ; frag = NEXT_RX(frag)) {
+               unsigned int frag_len = RX_BUFFER_SIZE;
+
+               if (offset + frag_len > len) {
+                       BUG_ON(frag != last_frag);
+                       frag_len = len - offset;
+               }
+               skb_copy_to_linear_data_offset(skb, offset,
+                                              (bp->rx_buffers +
+                                               (RX_BUFFER_SIZE * frag)),
+                                              frag_len);
+               offset += RX_BUFFER_SIZE;
+               bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
+               wmb();
+
+               if (frag == last_frag)
+                       break;
+       }
+
+       skb->protocol = eth_type_trans(skb, bp->dev);
+
+       bp->stats.rx_packets++;
+       bp->stats.rx_bytes += len;
+       dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
+               skb->len, skb->csum);
+       netif_receive_skb(skb);
+
+       return 0;
+}
+
+/* Mark DMA descriptors from begin up to and not including end as unused */
+static void discard_partial_frame(struct macb *bp, unsigned int begin,
+                                 unsigned int end)
+{
+       unsigned int frag;
+
+       for (frag = begin; frag != end; frag = NEXT_RX(frag))
+               bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
+       wmb();
+
+       /*
+        * When this happens, the hardware stats registers for
+        * whatever caused this is updated, so we don't have to record
+        * anything.
+        */
+}
+
+static int macb_rx(struct macb *bp, int budget)
+{
+       int received = 0;
+       unsigned int tail = bp->rx_tail;
+       int first_frag = -1;
+
+       for (; budget > 0; tail = NEXT_RX(tail)) {
+               u32 addr, ctrl;
+
+               rmb();
+               addr = bp->rx_ring[tail].addr;
+               ctrl = bp->rx_ring[tail].ctrl;
+
+               if (!(addr & MACB_BIT(RX_USED)))
+                       break;
+
+               if (ctrl & MACB_BIT(RX_SOF)) {
+                       if (first_frag != -1)
+                               discard_partial_frame(bp, first_frag, tail);
+                       first_frag = tail;
+               }
+
+               if (ctrl & MACB_BIT(RX_EOF)) {
+                       int dropped;
+                       BUG_ON(first_frag == -1);
+
+                       dropped = macb_rx_frame(bp, first_frag, tail);
+                       first_frag = -1;
+                       if (!dropped) {
+                               received++;
+                               budget--;
+                       }
+               }
+       }
+
+       if (first_frag != -1)
+               bp->rx_tail = first_frag;
+       else
+               bp->rx_tail = tail;
+
+       return received;
+}
+
+static int macb_poll(struct napi_struct *napi, int budget)
+{
+       struct macb *bp = container_of(napi, struct macb, napi);
+       int work_done;
+       u32 status;
+
+       status = macb_readl(bp, RSR);
+       macb_writel(bp, RSR, status);
+
+       work_done = 0;
+
+       dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
+               (unsigned long)status, budget);
+
+       work_done = macb_rx(bp, budget);
+       if (work_done < budget) {
+               napi_complete(napi);
+
+               /*
+                * We've done what we can to clean the buffers. Make sure we
+                * get notified when new packets arrive.
+                */
+               macb_writel(bp, IER, MACB_RX_INT_FLAGS);
+       }
+
+       /* TODO: Handle errors */
+
+       return work_done;
+}
+
+static irqreturn_t macb_interrupt(int irq, void *dev_id)
+{
+       struct net_device *dev = dev_id;
+       struct macb *bp = netdev_priv(dev);
+       u32 status;
+
+       status = macb_readl(bp, ISR);
+
+       if (unlikely(!status))
+               return IRQ_NONE;
+
+       spin_lock(&bp->lock);
+
+       while (status) {
+               /* close possible race with dev_close */
+               if (unlikely(!netif_running(dev))) {
+                       macb_writel(bp, IDR, ~0UL);
+                       break;
+               }
+
+               if (status & MACB_RX_INT_FLAGS) {
+                       /*
+                        * There's no point taking any more interrupts
+                        * until we have processed the buffers. The
+                        * scheduling call may fail if the poll routine
+                        * is already scheduled, so disable interrupts
+                        * now.
+                        */
+                       macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
+
+                       if (napi_schedule_prep(&bp->napi)) {
+                               dev_dbg(&bp->pdev->dev,
+                                       "scheduling RX softirq\n");
+                               __napi_schedule(&bp->napi);
+                       }
+               }
+
+               if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
+                           MACB_BIT(ISR_RLE)))
+                       macb_tx(bp);
+
+               /*
+                * Link change detection isn't possible with RMII, so we'll
+                * add that if/when we get our hands on a full-blown MII PHY.
+                */
+
+               if (status & MACB_BIT(ISR_ROVR)) {
+                       /* We missed at least one packet */
+                       bp->hw_stats.rx_overruns++;
+               }
+
+               if (status & MACB_BIT(HRESP)) {
+                       /*
+                        * TODO: Reset the hardware, and maybe move the printk
+                        * to a lower-priority context as well (work queue?)
+                        */
+                       printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
+                              dev->name);
+               }
+
+               status = macb_readl(bp, ISR);
+       }
+
+       spin_unlock(&bp->lock);
+
+       return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/*
+ * Polling receive - used by netconsole and other diagnostic tools
+ * to allow network i/o with interrupts disabled.
+ */
+static void macb_poll_controller(struct net_device *dev)
+{
+       unsigned long flags;
+
+       local_irq_save(flags);
+       macb_interrupt(dev->irq, dev);
+       local_irq_restore(flags);
+}
+#endif
+
+static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+       struct macb *bp = netdev_priv(dev);
+       dma_addr_t mapping;
+       unsigned int len, entry;
+       u32 ctrl;
+       unsigned long flags;
+
+#ifdef DEBUG
+       int i;
+       dev_dbg(&bp->pdev->dev,
+               "start_xmit: len %u head %p data %p tail %p end %p\n",
+               skb->len, skb->head, skb->data,
+               skb_tail_pointer(skb), skb_end_pointer(skb));
+       dev_dbg(&bp->pdev->dev,
+               "data:");
+       for (i = 0; i < 16; i++)
+               printk(" %02x", (unsigned int)skb->data[i]);
+       printk("\n");
+#endif
+
+       len = skb->len;
+       spin_lock_irqsave(&bp->lock, flags);
+
+       /* This is a hard error, log it. */
+       if (TX_BUFFS_AVAIL(bp) < 1) {
+               netif_stop_queue(dev);
+               spin_unlock_irqrestore(&bp->lock, flags);
+               dev_err(&bp->pdev->dev,
+                       "BUG! Tx Ring full when queue awake!\n");
+               dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
+                       bp->tx_head, bp->tx_tail);
+               return NETDEV_TX_BUSY;
+       }
+
+       entry = bp->tx_head;
+       dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
+       mapping = dma_map_single(&bp->pdev->dev, skb->data,
+                                len, DMA_TO_DEVICE);
+       bp->tx_skb[entry].skb = skb;
+       bp->tx_skb[entry].mapping = mapping;
+       dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
+               skb->data, (unsigned long)mapping);
+
+       ctrl = MACB_BF(TX_FRMLEN, len);
+       ctrl |= MACB_BIT(TX_LAST);
+       if (entry == (TX_RING_SIZE - 1))
+               ctrl |= MACB_BIT(TX_WRAP);
+
+       bp->tx_ring[entry].addr = mapping;
+       bp->tx_ring[entry].ctrl = ctrl;
+       wmb();
+
+       entry = NEXT_TX(entry);
+       bp->tx_head = entry;
+
+       skb_tx_timestamp(skb);
+
+       macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
+
+       if (TX_BUFFS_AVAIL(bp) < 1)
+               netif_stop_queue(dev);
+
+       spin_unlock_irqrestore(&bp->lock, flags);
+
+       return NETDEV_TX_OK;
+}
+
+static void macb_free_consistent(struct macb *bp)
+{
+       if (bp->tx_skb) {
+               kfree(bp->tx_skb);
+               bp->tx_skb = NULL;
+       }
+       if (bp->rx_ring) {
+               dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
+                                 bp->rx_ring, bp->rx_ring_dma);
+               bp->rx_ring = NULL;
+       }
+       if (bp->tx_ring) {
+               dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
+                                 bp->tx_ring, bp->tx_ring_dma);
+               bp->tx_ring = NULL;
+       }
+       if (bp->rx_buffers) {
+               dma_free_coherent(&bp->pdev->dev,
+                                 RX_RING_SIZE * RX_BUFFER_SIZE,
+                                 bp->rx_buffers, bp->rx_buffers_dma);
+               bp->rx_buffers = NULL;
+       }
+}
+
+static int macb_alloc_consistent(struct macb *bp)
+{
+       int size;
+
+       size = TX_RING_SIZE * sizeof(struct ring_info);
+       bp->tx_skb = kmalloc(size, GFP_KERNEL);
+       if (!bp->tx_skb)
+               goto out_err;
+
+       size = RX_RING_BYTES;
+       bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
+                                        &bp->rx_ring_dma, GFP_KERNEL);
+       if (!bp->rx_ring)
+               goto out_err;
+       dev_dbg(&bp->pdev->dev,
+               "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
+               size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
+
+       size = TX_RING_BYTES;
+       bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
+                                        &bp->tx_ring_dma, GFP_KERNEL);
+       if (!bp->tx_ring)
+               goto out_err;
+       dev_dbg(&bp->pdev->dev,
+               "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
+               size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
+
+       size = RX_RING_SIZE * RX_BUFFER_SIZE;
+       bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
+                                           &bp->rx_buffers_dma, GFP_KERNEL);
+       if (!bp->rx_buffers)
+               goto out_err;
+       dev_dbg(&bp->pdev->dev,
+               "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
+               size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
+
+       return 0;
+
+out_err:
+       macb_free_consistent(bp);
+       return -ENOMEM;
+}
+
+static void macb_init_rings(struct macb *bp)
+{
+       int i;
+       dma_addr_t addr;
+
+       addr = bp->rx_buffers_dma;
+       for (i = 0; i < RX_RING_SIZE; i++) {
+               bp->rx_ring[i].addr = addr;
+               bp->rx_ring[i].ctrl = 0;
+               addr += RX_BUFFER_SIZE;
+       }
+       bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
+
+       for (i = 0; i < TX_RING_SIZE; i++) {
+               bp->tx_ring[i].addr = 0;
+               bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
+       }
+       bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
+
+       bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
+}
+
+static void macb_reset_hw(struct macb *bp)
+{
+       /* Make sure we have the write buffer for ourselves */
+       wmb();
+
+       /*
+        * Disable RX and TX (XXX: Should we halt the transmission
+        * more gracefully?)
+        */
+       macb_writel(bp, NCR, 0);
+
+       /* Clear the stats registers (XXX: Update stats first?) */
+       macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
+
+       /* Clear all status flags */
+       macb_writel(bp, TSR, ~0UL);
+       macb_writel(bp, RSR, ~0UL);
+
+       /* Disable all interrupts */
+       macb_writel(bp, IDR, ~0UL);
+       macb_readl(bp, ISR);
+}
+
+static void macb_init_hw(struct macb *bp)
+{
+       u32 config;
+
+       macb_reset_hw(bp);
+       __macb_set_hwaddr(bp);
+
+       config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
+       config |= MACB_BIT(PAE);                /* PAuse Enable */
+       config |= MACB_BIT(DRFCS);              /* Discard Rx FCS */
+       config |= MACB_BIT(BIG);                /* Receive oversized frames */
+       if (bp->dev->flags & IFF_PROMISC)
+               config |= MACB_BIT(CAF);        /* Copy All Frames */
+       if (!(bp->dev->flags & IFF_BROADCAST))
+               config |= MACB_BIT(NBC);        /* No BroadCast */
+       macb_writel(bp, NCFGR, config);
+
+       /* Initialize TX and RX buffers */
+       macb_writel(bp, RBQP, bp->rx_ring_dma);
+       macb_writel(bp, TBQP, bp->tx_ring_dma);
+
+       /* Enable TX and RX */
+       macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
+
+       /* Enable interrupts */
+       macb_writel(bp, IER, (MACB_BIT(RCOMP)
+                             | MACB_BIT(RXUBR)
+                             | MACB_BIT(ISR_TUND)
+                             | MACB_BIT(ISR_RLE)
+                             | MACB_BIT(TXERR)
+                             | MACB_BIT(TCOMP)
+                             | MACB_BIT(ISR_ROVR)
+                             | MACB_BIT(HRESP)));
+
+}
+
+/*
+ * The hash address register is 64 bits long and takes up two
+ * locations in the memory map.  The least significant bits are stored
+ * in EMAC_HSL and the most significant bits in EMAC_HSH.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the
+ * network configuration register enable the reception of hash matched
+ * frames. The destination address is reduced to a 6 bit index into
+ * the 64 bit hash register using the following hash function.  The
+ * hash function is an exclusive or of every sixth bit of the
+ * destination address.
+ *
+ * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
+ * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
+ * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
+ * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
+ * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
+ * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
+ *
+ * da[0] represents the least significant bit of the first byte
+ * received, that is, the multicast/unicast indicator, and da[47]
+ * represents the most significant bit of the last byte received.  If
+ * the hash index, hi[n], points to a bit that is set in the hash
+ * register then the frame will be matched according to whether the
+ * frame is multicast or unicast.  A multicast match will be signalled
+ * if the multicast hash enable bit is set, da[0] is 1 and the hash
+ * index points to a bit set in the hash register.  A unicast match
+ * will be signalled if the unicast hash enable bit is set, da[0] is 0
+ * and the hash index points to a bit set in the hash register.  To
+ * receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the
+ * network configuration register.
+ */
+
+static inline int hash_bit_value(int bitnr, __u8 *addr)
+{
+       if (addr[bitnr / 8] & (1 << (bitnr % 8)))
+               return 1;
+       return 0;
+}
+
+/*
+ * Return the hash index value for the specified address.
+ */
+static int hash_get_index(__u8 *addr)
+{
+       int i, j, bitval;
+       int hash_index = 0;
+
+       for (j = 0; j < 6; j++) {
+               for (i = 0, bitval = 0; i < 8; i++)
+                       bitval ^= hash_bit_value(i*6 + j, addr);
+
+               hash_index |= (bitval << j);
+       }
+
+       return hash_index;
+}
+
+/*
+ * Add multicast addresses to the internal multicast-hash table.
+ */
+static void macb_sethashtable(struct net_device *dev)
+{
+       struct netdev_hw_addr *ha;
+       unsigned long mc_filter[2];
+       unsigned int bitnr;
+       struct macb *bp = netdev_priv(dev);
+
+       mc_filter[0] = mc_filter[1] = 0;
+
+       netdev_for_each_mc_addr(ha, dev) {
+               bitnr = hash_get_index(ha->addr);
+               mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
+       }
+
+       macb_writel(bp, HRB, mc_filter[0]);
+       macb_writel(bp, HRT, mc_filter[1]);
+}
+
+/*
+ * Enable/Disable promiscuous and multicast modes.
+ */
+static void macb_set_rx_mode(struct net_device *dev)
+{
+       unsigned long cfg;
+       struct macb *bp = netdev_priv(dev);
+
+       cfg = macb_readl(bp, NCFGR);
+
+       if (dev->flags & IFF_PROMISC)
+               /* Enable promiscuous mode */
+               cfg |= MACB_BIT(CAF);
+       else if (dev->flags & (~IFF_PROMISC))
+                /* Disable promiscuous mode */
+               cfg &= ~MACB_BIT(CAF);
+
+       if (dev->flags & IFF_ALLMULTI) {
+               /* Enable all multicast mode */
+               macb_writel(bp, HRB, -1);
+               macb_writel(bp, HRT, -1);
+               cfg |= MACB_BIT(NCFGR_MTI);
+       } else if (!netdev_mc_empty(dev)) {
+               /* Enable specific multicasts */
+               macb_sethashtable(dev);
+               cfg |= MACB_BIT(NCFGR_MTI);
+       } else if (dev->flags & (~IFF_ALLMULTI)) {
+               /* Disable all multicast mode */
+               macb_writel(bp, HRB, 0);
+               macb_writel(bp, HRT, 0);
+               cfg &= ~MACB_BIT(NCFGR_MTI);
+       }
+
+       macb_writel(bp, NCFGR, cfg);
+}
+
+static int macb_open(struct net_device *dev)
+{
+       struct macb *bp = netdev_priv(dev);
+       int err;
+
+       dev_dbg(&bp->pdev->dev, "open\n");
+
+       /* if the phy is not yet register, retry later*/
+       if (!bp->phy_dev)
+               return -EAGAIN;
+
+       if (!is_valid_ether_addr(dev->dev_addr))
+               return -EADDRNOTAVAIL;
+
+       err = macb_alloc_consistent(bp);
+       if (err) {
+               printk(KERN_ERR
+                      "%s: Unable to allocate DMA memory (error %d)\n",
+                      dev->name, err);
+               return err;
+       }
+
+       napi_enable(&bp->napi);
+
+       macb_init_rings(bp);
+       macb_init_hw(bp);
+
+       /* schedule a link state check */
+       phy_start(bp->phy_dev);
+
+       netif_start_queue(dev);
+
+       return 0;
+}
+
+static int macb_close(struct net_device *dev)
+{
+       struct macb *bp = netdev_priv(dev);
+       unsigned long flags;
+
+       netif_stop_queue(dev);
+       napi_disable(&bp->napi);
+
+       if (bp->phy_dev)
+               phy_stop(bp->phy_dev);
+
+       spin_lock_irqsave(&bp->lock, flags);
+       macb_reset_hw(bp);
+       netif_carrier_off(dev);
+       spin_unlock_irqrestore(&bp->lock, flags);
+
+       macb_free_consistent(bp);
+
+       return 0;
+}
+
+static struct net_device_stats *macb_get_stats(struct net_device *dev)
+{
+       struct macb *bp = netdev_priv(dev);
+       struct net_device_stats *nstat = &bp->stats;
+       struct macb_stats *hwstat = &bp->hw_stats;
+
+       /* read stats from hardware */
+       macb_update_stats(bp);
+
+       /* Convert HW stats into netdevice stats */
+       nstat->rx_errors = (hwstat->rx_fcs_errors +
+                           hwstat->rx_align_errors +
+                           hwstat->rx_resource_errors +
+                           hwstat->rx_overruns +
+                           hwstat->rx_oversize_pkts +
+                           hwstat->rx_jabbers +
+                           hwstat->rx_undersize_pkts +
+                           hwstat->sqe_test_errors +
+                           hwstat->rx_length_mismatch);
+       nstat->tx_errors = (hwstat->tx_late_cols +
+                           hwstat->tx_excessive_cols +
+                           hwstat->tx_underruns +
+                           hwstat->tx_carrier_errors);
+       nstat->collisions = (hwstat->tx_single_cols +
+                            hwstat->tx_multiple_cols +
+                            hwstat->tx_excessive_cols);
+       nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
+                                  hwstat->rx_jabbers +
+                                  hwstat->rx_undersize_pkts +
+                                  hwstat->rx_length_mismatch);
+       nstat->rx_over_errors = hwstat->rx_resource_errors +
+                                  hwstat->rx_overruns;
+       nstat->rx_crc_errors = hwstat->rx_fcs_errors;
+       nstat->rx_frame_errors = hwstat->rx_align_errors;
+       nstat->rx_fifo_errors = hwstat->rx_overruns;
+       /* XXX: What does "missed" mean? */
+       nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
+       nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
+       nstat->tx_fifo_errors = hwstat->tx_underruns;
+       /* Don't know about heartbeat or window errors... */
+
+       return nstat;
+}
+
+static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct macb *bp = netdev_priv(dev);
+       struct phy_device *phydev = bp->phy_dev;
+
+       if (!phydev)
+               return -ENODEV;
+
+       return phy_ethtool_gset(phydev, cmd);
+}
+
+static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+       struct macb *bp = netdev_priv(dev);
+       struct phy_device *phydev = bp->phy_dev;
+
+       if (!phydev)
+               return -ENODEV;
+
+       return phy_ethtool_sset(phydev, cmd);
+}
+
+static void macb_get_drvinfo(struct net_device *dev,
+                            struct ethtool_drvinfo *info)
+{
+       struct macb *bp = netdev_priv(dev);
+
+       strcpy(info->driver, bp->pdev->dev.driver->name);
+       strcpy(info->version, "$Revision: 1.14 $");
+       strcpy(info->bus_info, dev_name(&bp->pdev->dev));
+}
+
+static const struct ethtool_ops macb_ethtool_ops = {
+       .get_settings           = macb_get_settings,
+       .set_settings           = macb_set_settings,
+       .get_drvinfo            = macb_get_drvinfo,
+       .get_link               = ethtool_op_get_link,
+};
+
+static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+       struct macb *bp = netdev_priv(dev);
+       struct phy_device *phydev = bp->phy_dev;
+
+       if (!netif_running(dev))
+               return -EINVAL;
+
+       if (!phydev)
+               return -ENODEV;
+
+       return phy_mii_ioctl(phydev, rq, cmd);
+}
+
+static const struct net_device_ops macb_netdev_ops = {
+       .ndo_open               = macb_open,
+       .ndo_stop               = macb_close,
+       .ndo_start_xmit         = macb_start_xmit,
+       .ndo_set_multicast_list = macb_set_rx_mode,
+       .ndo_get_stats          = macb_get_stats,
+       .ndo_do_ioctl           = macb_ioctl,
+       .ndo_validate_addr      = eth_validate_addr,
+       .ndo_change_mtu         = eth_change_mtu,
+       .ndo_set_mac_address    = eth_mac_addr,
+#ifdef CONFIG_NET_POLL_CONTROLLER
+       .ndo_poll_controller    = macb_poll_controller,
+#endif
+};
+
+static int __init macb_probe(struct platform_device *pdev)
+{
+       struct eth_platform_data *pdata;
+       struct resource *regs;
+       struct net_device *dev;
+       struct macb *bp;
+       struct phy_device *phydev;
+       unsigned long pclk_hz;
+       u32 config;
+       int err = -ENXIO;
+
+       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       if (!regs) {
+               dev_err(&pdev->dev, "no mmio resource defined\n");
+               goto err_out;
+       }
+
+       err = -ENOMEM;
+       dev = alloc_etherdev(sizeof(*bp));
+       if (!dev) {
+               dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
+               goto err_out;
+       }
+
+       SET_NETDEV_DEV(dev, &pdev->dev);
+
+       /* TODO: Actually, we have some interesting features... */
+       dev->features |= 0;
+
+       bp = netdev_priv(dev);
+       bp->pdev = pdev;
+       bp->dev = dev;
+
+       spin_lock_init(&bp->lock);
+
+#if defined(CONFIG_ARCH_AT91)
+       bp->pclk = clk_get(&pdev->dev, "macb_clk");
+       if (IS_ERR(bp->pclk)) {
+               dev_err(&pdev->dev, "failed to get macb_clk\n");
+               goto err_out_free_dev;
+       }
+       clk_enable(bp->pclk);
+#else
+       bp->pclk = clk_get(&pdev->dev, "pclk");
+       if (IS_ERR(bp->pclk)) {
+               dev_err(&pdev->dev, "failed to get pclk\n");
+               goto err_out_free_dev;
+       }
+       bp->hclk = clk_get(&pdev->dev, "hclk");
+       if (IS_ERR(bp->hclk)) {
+               dev_err(&pdev->dev, "failed to get hclk\n");
+               goto err_out_put_pclk;
+       }
+
+       clk_enable(bp->pclk);
+       clk_enable(bp->hclk);
+#endif
+
+       bp->regs = ioremap(regs->start, resource_size(regs));
+       if (!bp->regs) {
+               dev_err(&pdev->dev, "failed to map registers, aborting.\n");
+               err = -ENOMEM;
+               goto err_out_disable_clocks;
+       }
+
+       dev->irq = platform_get_irq(pdev, 0);
+       err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
+       if (err) {
+               printk(KERN_ERR
+                      "%s: Unable to request IRQ %d (error %d)\n",
+                      dev->name, dev->irq, err);
+               goto err_out_iounmap;
+       }
+
+       dev->netdev_ops = &macb_netdev_ops;
+       netif_napi_add(dev, &bp->napi, macb_poll, 64);
+       dev->ethtool_ops = &macb_ethtool_ops;
+
+       dev->base_addr = regs->start;
+
+       /* Set MII management clock divider */
+       pclk_hz = clk_get_rate(bp->pclk);
+       if (pclk_hz <= 20000000)
+               config = MACB_BF(CLK, MACB_CLK_DIV8);
+       else if (pclk_hz <= 40000000)
+               config = MACB_BF(CLK, MACB_CLK_DIV16);
+       else if (pclk_hz <= 80000000)
+               config = MACB_BF(CLK, MACB_CLK_DIV32);
+       else
+               config = MACB_BF(CLK, MACB_CLK_DIV64);
+       macb_writel(bp, NCFGR, config);
+
+       macb_get_hwaddr(bp);
+       pdata = pdev->dev.platform_data;
+
+       if (pdata && pdata->is_rmii)
+#if defined(CONFIG_ARCH_AT91)
+               macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
+#else
+               macb_writel(bp, USRIO, 0);
+#endif
+       else
+#if defined(CONFIG_ARCH_AT91)
+               macb_writel(bp, USRIO, MACB_BIT(CLKEN));
+#else
+               macb_writel(bp, USRIO, MACB_BIT(MII));
+#endif
+
+       bp->tx_pending = DEF_TX_RING_PENDING;
+
+       err = register_netdev(dev);
+       if (err) {
+               dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
+               goto err_out_free_irq;
+       }
+
+       if (macb_mii_init(bp) != 0) {
+               goto err_out_unregister_netdev;
+       }
+
+       platform_set_drvdata(pdev, dev);
+
+       printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d (%pM)\n",
+              dev->name, dev->base_addr, dev->irq, dev->dev_addr);
+
+       phydev = bp->phy_dev;
+       printk(KERN_INFO "%s: attached PHY driver [%s] "
+               "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
+               phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
+
+       return 0;
+
+err_out_unregister_netdev:
+       unregister_netdev(dev);
+err_out_free_irq:
+       free_irq(dev->irq, dev);
+err_out_iounmap:
+       iounmap(bp->regs);
+err_out_disable_clocks:
+#ifndef CONFIG_ARCH_AT91
+       clk_disable(bp->hclk);
+       clk_put(bp->hclk);
+#endif
+       clk_disable(bp->pclk);
+#ifndef CONFIG_ARCH_AT91
+err_out_put_pclk:
+#endif
+       clk_put(bp->pclk);
+err_out_free_dev:
+       free_netdev(dev);
+err_out:
+       platform_set_drvdata(pdev, NULL);
+       return err;
+}
+
+static int __exit macb_remove(struct platform_device *pdev)
+{
+       struct net_device *dev;
+       struct macb *bp;
+
+       dev = platform_get_drvdata(pdev);
+
+       if (dev) {
+               bp = netdev_priv(dev);
+               if (bp->phy_dev)
+                       phy_disconnect(bp->phy_dev);
+               mdiobus_unregister(bp->mii_bus);
+               kfree(bp->mii_bus->irq);
+               mdiobus_free(bp->mii_bus);
+               unregister_netdev(dev);
+               free_irq(dev->irq, dev);
+               iounmap(bp->regs);
+#ifndef CONFIG_ARCH_AT91
+               clk_disable(bp->hclk);
+               clk_put(bp->hclk);
+#endif
+               clk_disable(bp->pclk);
+               clk_put(bp->pclk);
+               free_netdev(dev);
+               platform_set_drvdata(pdev, NULL);
+       }
+
+       return 0;
+}
+
+#ifdef CONFIG_PM
+static int macb_suspend(struct platform_device *pdev, pm_message_t state)
+{
+       struct net_device *netdev = platform_get_drvdata(pdev);
+       struct macb *bp = netdev_priv(netdev);
+
+       netif_device_detach(netdev);
+
+#ifndef CONFIG_ARCH_AT91
+       clk_disable(bp->hclk);
+#endif
+       clk_disable(bp->pclk);
+
+       return 0;
+}
+
+static int macb_resume(struct platform_device *pdev)
+{
+       struct net_device *netdev = platform_get_drvdata(pdev);
+       struct macb *bp = netdev_priv(netdev);
+
+       clk_enable(bp->pclk);
+#ifndef CONFIG_ARCH_AT91
+       clk_enable(bp->hclk);
+#endif
+
+       netif_device_attach(netdev);
+
+       return 0;
+}
+#else
+#define macb_suspend   NULL
+#define macb_resume    NULL
+#endif
+
+static struct platform_driver macb_driver = {
+       .remove         = __exit_p(macb_remove),
+       .suspend        = macb_suspend,
+       .resume         = macb_resume,
+       .driver         = {
+               .name           = "macb",
+               .owner  = THIS_MODULE,
+       },
+};
+
+static int __init macb_init(void)
+{
+       return platform_driver_probe(&macb_driver, macb_probe);
+}
+
+static void __exit macb_exit(void)
+{
+       platform_driver_unregister(&macb_driver);
+}
+
+module_init(macb_init);
+module_exit(macb_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
+MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
+MODULE_ALIAS("platform:macb");
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h
new file mode 100644 (file)
index 0000000..d3212f6
--- /dev/null
@@ -0,0 +1,394 @@
+/*
+ * Atmel MACB Ethernet Controller driver
+ *
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _MACB_H
+#define _MACB_H
+
+/* MACB register offsets */
+#define MACB_NCR                               0x0000
+#define MACB_NCFGR                             0x0004
+#define MACB_NSR                               0x0008
+#define MACB_TSR                               0x0014
+#define MACB_RBQP                              0x0018
+#define MACB_TBQP                              0x001c
+#define MACB_RSR                               0x0020
+#define MACB_ISR                               0x0024
+#define MACB_IER                               0x0028
+#define MACB_IDR                               0x002c
+#define MACB_IMR                               0x0030
+#define MACB_MAN                               0x0034
+#define MACB_PTR                               0x0038
+#define MACB_PFR                               0x003c
+#define MACB_FTO                               0x0040
+#define MACB_SCF                               0x0044
+#define MACB_MCF                               0x0048
+#define MACB_FRO                               0x004c
+#define MACB_FCSE                              0x0050
+#define MACB_ALE                               0x0054
+#define MACB_DTF                               0x0058
+#define MACB_LCOL                              0x005c
+#define MACB_EXCOL                             0x0060
+#define MACB_TUND                              0x0064
+#define MACB_CSE                               0x0068
+#define MACB_RRE                               0x006c
+#define MACB_ROVR                              0x0070
+#define MACB_RSE                               0x0074
+#define MACB_ELE                               0x0078
+#define MACB_RJA                               0x007c
+#define MACB_USF                               0x0080
+#define MACB_STE                               0x0084
+#define MACB_RLE                               0x0088
+#define MACB_TPF                               0x008c
+#define MACB_HRB                               0x0090
+#define MACB_HRT                               0x0094
+#define MACB_SA1B                              0x0098
+#define MACB_SA1T                              0x009c
+#define MACB_SA2B                              0x00a0
+#define MACB_SA2T                              0x00a4
+#define MACB_SA3B                              0x00a8
+#define MACB_SA3T                              0x00ac
+#define MACB_SA4B                              0x00b0
+#define MACB_SA4T                              0x00b4
+#define MACB_TID                               0x00b8
+#define MACB_TPQ                               0x00bc
+#define MACB_USRIO                             0x00c0
+#define MACB_WOL                               0x00c4
+
+/* Bitfields in NCR */
+#define MACB_LB_OFFSET                         0
+#define MACB_LB_SIZE                           1
+#define MACB_LLB_OFFSET                                1
+#define MACB_LLB_SIZE                          1
+#define MACB_RE_OFFSET                         2
+#define MACB_RE_SIZE                           1
+#define MACB_TE_OFFSET                         3
+#define MACB_TE_SIZE                           1
+#define MACB_MPE_OFFSET                                4
+#define MACB_MPE_SIZE                          1
+#define MACB_CLRSTAT_OFFSET                    5
+#define MACB_CLRSTAT_SIZE                      1
+#define MACB_INCSTAT_OFFSET                    6
+#define MACB_INCSTAT_SIZE                      1
+#define MACB_WESTAT_OFFSET                     7
+#define MACB_WESTAT_SIZE                       1
+#define MACB_BP_OFFSET                         8
+#define MACB_BP_SIZE                           1
+#define MACB_TSTART_OFFSET                     9
+#define MACB_TSTART_SIZE                       1
+#define MACB_THALT_OFFSET                      10
+#define MACB_THALT_SIZE                                1
+#define MACB_NCR_TPF_OFFSET                    11
+#define MACB_NCR_TPF_SIZE                      1
+#define MACB_TZQ_OFFSET                                12
+#define MACB_TZQ_SIZE                          1
+
+/* Bitfields in NCFGR */
+#define MACB_SPD_OFFSET                                0
+#define MACB_SPD_SIZE                          1
+#define MACB_FD_OFFSET                         1
+#define MACB_FD_SIZE                           1
+#define MACB_BIT_RATE_OFFSET                   2
+#define MACB_BIT_RATE_SIZE                     1
+#define MACB_JFRAME_OFFSET                     3
+#define MACB_JFRAME_SIZE                       1
+#define MACB_CAF_OFFSET                                4
+#define MACB_CAF_SIZE                          1
+#define MACB_NBC_OFFSET                                5
+#define MACB_NBC_SIZE                          1
+#define MACB_NCFGR_MTI_OFFSET                  6
+#define MACB_NCFGR_MTI_SIZE                    1
+#define MACB_UNI_OFFSET                                7
+#define MACB_UNI_SIZE                          1
+#define MACB_BIG_OFFSET                                8
+#define MACB_BIG_SIZE                          1
+#define MACB_EAE_OFFSET                                9
+#define MACB_EAE_SIZE                          1
+#define MACB_CLK_OFFSET                                10
+#define MACB_CLK_SIZE                          2
+#define MACB_RTY_OFFSET                                12
+#define MACB_RTY_SIZE                          1
+#define MACB_PAE_OFFSET                                13
+#define MACB_PAE_SIZE                          1
+#define MACB_RBOF_OFFSET                       14
+#define MACB_RBOF_SIZE                         2
+#define MACB_RLCE_OFFSET                       16
+#define MACB_RLCE_SIZE                         1
+#define MACB_DRFCS_OFFSET                      17
+#define MACB_DRFCS_SIZE                                1
+#define MACB_EFRHD_OFFSET                      18
+#define MACB_EFRHD_SIZE                                1
+#define MACB_IRXFCS_OFFSET                     19
+#define MACB_IRXFCS_SIZE                       1
+
+/* Bitfields in NSR */
+#define MACB_NSR_LINK_OFFSET                   0
+#define MACB_NSR_LINK_SIZE                     1
+#define MACB_MDIO_OFFSET                       1
+#define MACB_MDIO_SIZE                         1
+#define MACB_IDLE_OFFSET                       2
+#define MACB_IDLE_SIZE                         1
+
+/* Bitfields in TSR */
+#define MACB_UBR_OFFSET                                0
+#define MACB_UBR_SIZE                          1
+#define MACB_COL_OFFSET                                1
+#define MACB_COL_SIZE                          1
+#define MACB_TSR_RLE_OFFSET                    2
+#define MACB_TSR_RLE_SIZE                      1
+#define MACB_TGO_OFFSET                                3
+#define MACB_TGO_SIZE                          1
+#define MACB_BEX_OFFSET                                4
+#define MACB_BEX_SIZE                          1
+#define MACB_COMP_OFFSET                       5
+#define MACB_COMP_SIZE                         1
+#define MACB_UND_OFFSET                                6
+#define MACB_UND_SIZE                          1
+
+/* Bitfields in RSR */
+#define MACB_BNA_OFFSET                                0
+#define MACB_BNA_SIZE                          1
+#define MACB_REC_OFFSET                                1
+#define MACB_REC_SIZE                          1
+#define MACB_OVR_OFFSET                                2
+#define MACB_OVR_SIZE                          1
+
+/* Bitfields in ISR/IER/IDR/IMR */
+#define MACB_MFD_OFFSET                                0
+#define MACB_MFD_SIZE                          1
+#define MACB_RCOMP_OFFSET                      1
+#define MACB_RCOMP_SIZE                                1
+#define MACB_RXUBR_OFFSET                      2
+#define MACB_RXUBR_SIZE                                1
+#define MACB_TXUBR_OFFSET                      3
+#define MACB_TXUBR_SIZE                                1
+#define MACB_ISR_TUND_OFFSET                   4
+#define MACB_ISR_TUND_SIZE                     1
+#define MACB_ISR_RLE_OFFSET                    5
+#define MACB_ISR_RLE_SIZE                      1
+#define MACB_TXERR_OFFSET                      6
+#define MACB_TXERR_SIZE                                1
+#define MACB_TCOMP_OFFSET                      7
+#define MACB_TCOMP_SIZE                                1
+#define MACB_ISR_LINK_OFFSET                   9
+#define MACB_ISR_LINK_SIZE                     1
+#define MACB_ISR_ROVR_OFFSET                   10
+#define MACB_ISR_ROVR_SIZE                     1
+#define MACB_HRESP_OFFSET                      11
+#define MACB_HRESP_SIZE                                1
+#define MACB_PFR_OFFSET                                12
+#define MACB_PFR_SIZE                          1
+#define MACB_PTZ_OFFSET                                13
+#define MACB_PTZ_SIZE                          1
+
+/* Bitfields in MAN */
+#define MACB_DATA_OFFSET                       0
+#define MACB_DATA_SIZE                         16
+#define MACB_CODE_OFFSET                       16
+#define MACB_CODE_SIZE                         2
+#define MACB_REGA_OFFSET                       18
+#define MACB_REGA_SIZE                         5
+#define MACB_PHYA_OFFSET                       23
+#define MACB_PHYA_SIZE                         5
+#define MACB_RW_OFFSET                         28
+#define MACB_RW_SIZE                           2
+#define MACB_SOF_OFFSET                                30
+#define MACB_SOF_SIZE                          2
+
+/* Bitfields in USRIO (AVR32) */
+#define MACB_MII_OFFSET                                0
+#define MACB_MII_SIZE                          1
+#define MACB_EAM_OFFSET                                1
+#define MACB_EAM_SIZE                          1
+#define MACB_TX_PAUSE_OFFSET                   2
+#define MACB_TX_PAUSE_SIZE                     1
+#define MACB_TX_PAUSE_ZERO_OFFSET              3
+#define MACB_TX_PAUSE_ZERO_SIZE                        1
+
+/* Bitfields in USRIO (AT91) */
+#define MACB_RMII_OFFSET                       0
+#define MACB_RMII_SIZE                         1
+#define MACB_CLKEN_OFFSET                      1
+#define MACB_CLKEN_SIZE                                1
+
+/* Bitfields in WOL */
+#define MACB_IP_OFFSET                         0
+#define MACB_IP_SIZE                           16
+#define MACB_MAG_OFFSET                                16
+#define MACB_MAG_SIZE                          1
+#define MACB_ARP_OFFSET                                17
+#define MACB_ARP_SIZE                          1
+#define MACB_SA1_OFFSET                                18
+#define MACB_SA1_SIZE                          1
+#define MACB_WOL_MTI_OFFSET                    19
+#define MACB_WOL_MTI_SIZE                      1
+
+/* Constants for CLK */
+#define MACB_CLK_DIV8                          0
+#define MACB_CLK_DIV16                         1
+#define MACB_CLK_DIV32                         2
+#define MACB_CLK_DIV64                         3
+
+/* Constants for MAN register */
+#define MACB_MAN_SOF                           1
+#define MACB_MAN_WRITE                         1
+#define MACB_MAN_READ                          2
+#define MACB_MAN_CODE                          2
+
+/* Bit manipulation macros */
+#define MACB_BIT(name)                                 \
+       (1 << MACB_##name##_OFFSET)
+#define MACB_BF(name,value)                            \
+       (((value) & ((1 << MACB_##name##_SIZE) - 1))    \
+        << MACB_##name##_OFFSET)
+#define MACB_BFEXT(name,value)\
+       (((value) >> MACB_##name##_OFFSET)              \
+        & ((1 << MACB_##name##_SIZE) - 1))
+#define MACB_BFINS(name,value,old)                     \
+       (((old) & ~(((1 << MACB_##name##_SIZE) - 1)     \
+                   << MACB_##name##_OFFSET))           \
+        | MACB_BF(name,value))
+
+/* Register access macros */
+#define macb_readl(port,reg)                           \
+       __raw_readl((port)->regs + MACB_##reg)
+#define macb_writel(port,reg,value)                    \
+       __raw_writel((value), (port)->regs + MACB_##reg)
+
+struct dma_desc {
+       u32     addr;
+       u32     ctrl;
+};
+
+/* DMA descriptor bitfields */
+#define MACB_RX_USED_OFFSET                    0
+#define MACB_RX_USED_SIZE                      1
+#define MACB_RX_WRAP_OFFSET                    1
+#define MACB_RX_WRAP_SIZE                      1
+#define MACB_RX_WADDR_OFFSET                   2
+#define MACB_RX_WADDR_SIZE                     30
+
+#define MACB_RX_FRMLEN_OFFSET                  0
+#define MACB_RX_FRMLEN_SIZE                    12
+#define MACB_RX_OFFSET_OFFSET                  12
+#define MACB_RX_OFFSET_SIZE                    2
+#define MACB_RX_SOF_OFFSET                     14
+#define MACB_RX_SOF_SIZE                       1
+#define MACB_RX_EOF_OFFSET                     15
+#define MACB_RX_EOF_SIZE                       1
+#define MACB_RX_CFI_OFFSET                     16
+#define MACB_RX_CFI_SIZE                       1
+#define MACB_RX_VLAN_PRI_OFFSET                        17
+#define MACB_RX_VLAN_PRI_SIZE                  3
+#define MACB_RX_PRI_TAG_OFFSET                 20
+#define MACB_RX_PRI_TAG_SIZE                   1
+#define MACB_RX_VLAN_TAG_OFFSET                        21
+#define MACB_RX_VLAN_TAG_SIZE                  1
+#define MACB_RX_TYPEID_MATCH_OFFSET            22
+#define MACB_RX_TYPEID_MATCH_SIZE              1
+#define MACB_RX_SA4_MATCH_OFFSET               23
+#define MACB_RX_SA4_MATCH_SIZE                 1
+#define MACB_RX_SA3_MATCH_OFFSET               24
+#define MACB_RX_SA3_MATCH_SIZE                 1
+#define MACB_RX_SA2_MATCH_OFFSET               25
+#define MACB_RX_SA2_MATCH_SIZE                 1
+#define MACB_RX_SA1_MATCH_OFFSET               26
+#define MACB_RX_SA1_MATCH_SIZE                 1
+#define MACB_RX_EXT_MATCH_OFFSET               28
+#define MACB_RX_EXT_MATCH_SIZE                 1
+#define MACB_RX_UHASH_MATCH_OFFSET             29
+#define MACB_RX_UHASH_MATCH_SIZE               1
+#define MACB_RX_MHASH_MATCH_OFFSET             30
+#define MACB_RX_MHASH_MATCH_SIZE               1
+#define MACB_RX_BROADCAST_OFFSET               31
+#define MACB_RX_BROADCAST_SIZE                 1
+
+#define MACB_TX_FRMLEN_OFFSET                  0
+#define MACB_TX_FRMLEN_SIZE                    11
+#define MACB_TX_LAST_OFFSET                    15
+#define MACB_TX_LAST_SIZE                      1
+#define MACB_TX_NOCRC_OFFSET                   16
+#define MACB_TX_NOCRC_SIZE                     1
+#define MACB_TX_BUF_EXHAUSTED_OFFSET           27
+#define MACB_TX_BUF_EXHAUSTED_SIZE             1
+#define MACB_TX_UNDERRUN_OFFSET                        28
+#define MACB_TX_UNDERRUN_SIZE                  1
+#define MACB_TX_ERROR_OFFSET                   29
+#define MACB_TX_ERROR_SIZE                     1
+#define MACB_TX_WRAP_OFFSET                    30
+#define MACB_TX_WRAP_SIZE                      1
+#define MACB_TX_USED_OFFSET                    31
+#define MACB_TX_USED_SIZE                      1
+
+struct ring_info {
+       struct sk_buff          *skb;
+       dma_addr_t              mapping;
+};
+
+/*
+ * Hardware-collected statistics. Used when updating the network
+ * device stats by a periodic timer.
+ */
+struct macb_stats {
+       u32     rx_pause_frames;
+       u32     tx_ok;
+       u32     tx_single_cols;
+       u32     tx_multiple_cols;
+       u32     rx_ok;
+       u32     rx_fcs_errors;
+       u32     rx_align_errors;
+       u32     tx_deferred;
+       u32     tx_late_cols;
+       u32     tx_excessive_cols;
+       u32     tx_underruns;
+       u32     tx_carrier_errors;
+       u32     rx_resource_errors;
+       u32     rx_overruns;
+       u32     rx_symbol_errors;
+       u32     rx_oversize_pkts;
+       u32     rx_jabbers;
+       u32     rx_undersize_pkts;
+       u32     sqe_test_errors;
+       u32     rx_length_mismatch;
+       u32     tx_pause_frames;
+};
+
+struct macb {
+       void __iomem            *regs;
+
+       unsigned int            rx_tail;
+       struct dma_desc         *rx_ring;
+       void                    *rx_buffers;
+
+       unsigned int            tx_head, tx_tail;
+       struct dma_desc         *tx_ring;
+       struct ring_info        *tx_skb;
+
+       spinlock_t              lock;
+       struct platform_device  *pdev;
+       struct clk              *pclk;
+       struct clk              *hclk;
+       struct net_device       *dev;
+       struct napi_struct      napi;
+       struct net_device_stats stats;
+       struct macb_stats       hw_stats;
+
+       dma_addr_t              rx_ring_dma;
+       dma_addr_t              tx_ring_dma;
+       dma_addr_t              rx_buffers_dma;
+
+       unsigned int            rx_pending, tx_pending;
+
+       struct mii_bus          *mii_bus;
+       struct phy_device       *phy_dev;
+       unsigned int            link;
+       unsigned int            speed;
+       unsigned int            duplex;
+};
+
+#endif /* _MACB_H */
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
deleted file mode 100644 (file)
index dc4e305..0000000
+++ /dev/null
@@ -1,1366 +0,0 @@
-/*
- * Atmel MACB Ethernet Controller driver
- *
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/phy.h>
-
-#include <mach/board.h>
-#include <mach/cpu.h>
-
-#include "macb.h"
-
-#define RX_BUFFER_SIZE         128
-#define RX_RING_SIZE           512
-#define RX_RING_BYTES          (sizeof(struct dma_desc) * RX_RING_SIZE)
-
-/* Make the IP header word-aligned (the ethernet header is 14 bytes) */
-#define RX_OFFSET              2
-
-#define TX_RING_SIZE           128
-#define DEF_TX_RING_PENDING    (TX_RING_SIZE - 1)
-#define TX_RING_BYTES          (sizeof(struct dma_desc) * TX_RING_SIZE)
-
-#define TX_RING_GAP(bp)                                                \
-       (TX_RING_SIZE - (bp)->tx_pending)
-#define TX_BUFFS_AVAIL(bp)                                     \
-       (((bp)->tx_tail <= (bp)->tx_head) ?                     \
-        (bp)->tx_tail + (bp)->tx_pending - (bp)->tx_head :     \
-        (bp)->tx_tail - (bp)->tx_head - TX_RING_GAP(bp))
-#define NEXT_TX(n)             (((n) + 1) & (TX_RING_SIZE - 1))
-
-#define NEXT_RX(n)             (((n) + 1) & (RX_RING_SIZE - 1))
-
-/* minimum number of free TX descriptors before waking up TX process */
-#define MACB_TX_WAKEUP_THRESH  (TX_RING_SIZE / 4)
-
-#define MACB_RX_INT_FLAGS      (MACB_BIT(RCOMP) | MACB_BIT(RXUBR)      \
-                                | MACB_BIT(ISR_ROVR))
-
-static void __macb_set_hwaddr(struct macb *bp)
-{
-       u32 bottom;
-       u16 top;
-
-       bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
-       macb_writel(bp, SA1B, bottom);
-       top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
-       macb_writel(bp, SA1T, top);
-}
-
-static void __init macb_get_hwaddr(struct macb *bp)
-{
-       u32 bottom;
-       u16 top;
-       u8 addr[6];
-
-       bottom = macb_readl(bp, SA1B);
-       top = macb_readl(bp, SA1T);
-
-       addr[0] = bottom & 0xff;
-       addr[1] = (bottom >> 8) & 0xff;
-       addr[2] = (bottom >> 16) & 0xff;
-       addr[3] = (bottom >> 24) & 0xff;
-       addr[4] = top & 0xff;
-       addr[5] = (top >> 8) & 0xff;
-
-       if (is_valid_ether_addr(addr)) {
-               memcpy(bp->dev->dev_addr, addr, sizeof(addr));
-       } else {
-               dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
-               random_ether_addr(bp->dev->dev_addr);
-       }
-}
-
-static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
-{
-       struct macb *bp = bus->priv;
-       int value;
-
-       macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
-                             | MACB_BF(RW, MACB_MAN_READ)
-                             | MACB_BF(PHYA, mii_id)
-                             | MACB_BF(REGA, regnum)
-                             | MACB_BF(CODE, MACB_MAN_CODE)));
-
-       /* wait for end of transfer */
-       while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
-               cpu_relax();
-
-       value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
-
-       return value;
-}
-
-static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
-                          u16 value)
-{
-       struct macb *bp = bus->priv;
-
-       macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
-                             | MACB_BF(RW, MACB_MAN_WRITE)
-                             | MACB_BF(PHYA, mii_id)
-                             | MACB_BF(REGA, regnum)
-                             | MACB_BF(CODE, MACB_MAN_CODE)
-                             | MACB_BF(DATA, value)));
-
-       /* wait for end of transfer */
-       while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
-               cpu_relax();
-
-       return 0;
-}
-
-static int macb_mdio_reset(struct mii_bus *bus)
-{
-       return 0;
-}
-
-static void macb_handle_link_change(struct net_device *dev)
-{
-       struct macb *bp = netdev_priv(dev);
-       struct phy_device *phydev = bp->phy_dev;
-       unsigned long flags;
-
-       int status_change = 0;
-
-       spin_lock_irqsave(&bp->lock, flags);
-
-       if (phydev->link) {
-               if ((bp->speed != phydev->speed) ||
-                   (bp->duplex != phydev->duplex)) {
-                       u32 reg;
-
-                       reg = macb_readl(bp, NCFGR);
-                       reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
-
-                       if (phydev->duplex)
-                               reg |= MACB_BIT(FD);
-                       if (phydev->speed == SPEED_100)
-                               reg |= MACB_BIT(SPD);
-
-                       macb_writel(bp, NCFGR, reg);
-
-                       bp->speed = phydev->speed;
-                       bp->duplex = phydev->duplex;
-                       status_change = 1;
-               }
-       }
-
-       if (phydev->link != bp->link) {
-               if (!phydev->link) {
-                       bp->speed = 0;
-                       bp->duplex = -1;
-               }
-               bp->link = phydev->link;
-
-               status_change = 1;
-       }
-
-       spin_unlock_irqrestore(&bp->lock, flags);
-
-       if (status_change) {
-               if (phydev->link)
-                       printk(KERN_INFO "%s: link up (%d/%s)\n",
-                              dev->name, phydev->speed,
-                              DUPLEX_FULL == phydev->duplex ? "Full":"Half");
-               else
-                       printk(KERN_INFO "%s: link down\n", dev->name);
-       }
-}
-
-/* based on au1000_eth. c*/
-static int macb_mii_probe(struct net_device *dev)
-{
-       struct macb *bp = netdev_priv(dev);
-       struct phy_device *phydev;
-       struct eth_platform_data *pdata;
-       int ret;
-
-       phydev = phy_find_first(bp->mii_bus);
-       if (!phydev) {
-               printk (KERN_ERR "%s: no PHY found\n", dev->name);
-               return -1;
-       }
-
-       pdata = bp->pdev->dev.platform_data;
-       /* TODO : add pin_irq */
-
-       /* attach the mac to the phy */
-       ret = phy_connect_direct(dev, phydev, &macb_handle_link_change, 0,
-                                pdata && pdata->is_rmii ?
-                                PHY_INTERFACE_MODE_RMII :
-                                PHY_INTERFACE_MODE_MII);
-       if (ret) {
-               printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
-               return ret;
-       }
-
-       /* mask with MAC supported features */
-       phydev->supported &= PHY_BASIC_FEATURES;
-
-       phydev->advertising = phydev->supported;
-
-       bp->link = 0;
-       bp->speed = 0;
-       bp->duplex = -1;
-       bp->phy_dev = phydev;
-
-       return 0;
-}
-
-static int macb_mii_init(struct macb *bp)
-{
-       struct eth_platform_data *pdata;
-       int err = -ENXIO, i;
-
-       /* Enable management port */
-       macb_writel(bp, NCR, MACB_BIT(MPE));
-
-       bp->mii_bus = mdiobus_alloc();
-       if (bp->mii_bus == NULL) {
-               err = -ENOMEM;
-               goto err_out;
-       }
-
-       bp->mii_bus->name = "MACB_mii_bus";
-       bp->mii_bus->read = &macb_mdio_read;
-       bp->mii_bus->write = &macb_mdio_write;
-       bp->mii_bus->reset = &macb_mdio_reset;
-       snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", bp->pdev->id);
-       bp->mii_bus->priv = bp;
-       bp->mii_bus->parent = &bp->dev->dev;
-       pdata = bp->pdev->dev.platform_data;
-
-       if (pdata)
-               bp->mii_bus->phy_mask = pdata->phy_mask;
-
-       bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
-       if (!bp->mii_bus->irq) {
-               err = -ENOMEM;
-               goto err_out_free_mdiobus;
-       }
-
-       for (i = 0; i < PHY_MAX_ADDR; i++)
-               bp->mii_bus->irq[i] = PHY_POLL;
-
-       dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
-
-       if (mdiobus_register(bp->mii_bus))
-               goto err_out_free_mdio_irq;
-
-       if (macb_mii_probe(bp->dev) != 0) {
-               goto err_out_unregister_bus;
-       }
-
-       return 0;
-
-err_out_unregister_bus:
-       mdiobus_unregister(bp->mii_bus);
-err_out_free_mdio_irq:
-       kfree(bp->mii_bus->irq);
-err_out_free_mdiobus:
-       mdiobus_free(bp->mii_bus);
-err_out:
-       return err;
-}
-
-static void macb_update_stats(struct macb *bp)
-{
-       u32 __iomem *reg = bp->regs + MACB_PFR;
-       u32 *p = &bp->hw_stats.rx_pause_frames;
-       u32 *end = &bp->hw_stats.tx_pause_frames + 1;
-
-       WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
-
-       for(; p < end; p++, reg++)
-               *p += __raw_readl(reg);
-}
-
-static void macb_tx(struct macb *bp)
-{
-       unsigned int tail;
-       unsigned int head;
-       u32 status;
-
-       status = macb_readl(bp, TSR);
-       macb_writel(bp, TSR, status);
-
-       dev_dbg(&bp->pdev->dev, "macb_tx status = %02lx\n",
-               (unsigned long)status);
-
-       if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) {
-               int i;
-               printk(KERN_ERR "%s: TX %s, resetting buffers\n",
-                       bp->dev->name, status & MACB_BIT(UND) ?
-                       "underrun" : "retry limit exceeded");
-
-               /* Transfer ongoing, disable transmitter, to avoid confusion */
-               if (status & MACB_BIT(TGO))
-                       macb_writel(bp, NCR, macb_readl(bp, NCR) & ~MACB_BIT(TE));
-
-               head = bp->tx_head;
-
-               /*Mark all the buffer as used to avoid sending a lost buffer*/
-               for (i = 0; i < TX_RING_SIZE; i++)
-                       bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
-
-               /* Add wrap bit */
-               bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
-
-               /* free transmit buffer in upper layer*/
-               for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
-                       struct ring_info *rp = &bp->tx_skb[tail];
-                       struct sk_buff *skb = rp->skb;
-
-                       BUG_ON(skb == NULL);
-
-                       rmb();
-
-                       dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
-                                                        DMA_TO_DEVICE);
-                       rp->skb = NULL;
-                       dev_kfree_skb_irq(skb);
-               }
-
-               bp->tx_head = bp->tx_tail = 0;
-
-               /* Enable the transmitter again */
-               if (status & MACB_BIT(TGO))
-                       macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
-       }
-
-       if (!(status & MACB_BIT(COMP)))
-               /*
-                * This may happen when a buffer becomes complete
-                * between reading the ISR and scanning the
-                * descriptors.  Nothing to worry about.
-                */
-               return;
-
-       head = bp->tx_head;
-       for (tail = bp->tx_tail; tail != head; tail = NEXT_TX(tail)) {
-               struct ring_info *rp = &bp->tx_skb[tail];
-               struct sk_buff *skb = rp->skb;
-               u32 bufstat;
-
-               BUG_ON(skb == NULL);
-
-               rmb();
-               bufstat = bp->tx_ring[tail].ctrl;
-
-               if (!(bufstat & MACB_BIT(TX_USED)))
-                       break;
-
-               dev_dbg(&bp->pdev->dev, "skb %u (data %p) TX complete\n",
-                       tail, skb->data);
-               dma_unmap_single(&bp->pdev->dev, rp->mapping, skb->len,
-                                DMA_TO_DEVICE);
-               bp->stats.tx_packets++;
-               bp->stats.tx_bytes += skb->len;
-               rp->skb = NULL;
-               dev_kfree_skb_irq(skb);
-       }
-
-       bp->tx_tail = tail;
-       if (netif_queue_stopped(bp->dev) &&
-           TX_BUFFS_AVAIL(bp) > MACB_TX_WAKEUP_THRESH)
-               netif_wake_queue(bp->dev);
-}
-
-static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
-                        unsigned int last_frag)
-{
-       unsigned int len;
-       unsigned int frag;
-       unsigned int offset = 0;
-       struct sk_buff *skb;
-
-       len = MACB_BFEXT(RX_FRMLEN, bp->rx_ring[last_frag].ctrl);
-
-       dev_dbg(&bp->pdev->dev, "macb_rx_frame frags %u - %u (len %u)\n",
-               first_frag, last_frag, len);
-
-       skb = dev_alloc_skb(len + RX_OFFSET);
-       if (!skb) {
-               bp->stats.rx_dropped++;
-               for (frag = first_frag; ; frag = NEXT_RX(frag)) {
-                       bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
-                       if (frag == last_frag)
-                               break;
-               }
-               wmb();
-               return 1;
-       }
-
-       skb_reserve(skb, RX_OFFSET);
-       skb_checksum_none_assert(skb);
-       skb_put(skb, len);
-
-       for (frag = first_frag; ; frag = NEXT_RX(frag)) {
-               unsigned int frag_len = RX_BUFFER_SIZE;
-
-               if (offset + frag_len > len) {
-                       BUG_ON(frag != last_frag);
-                       frag_len = len - offset;
-               }
-               skb_copy_to_linear_data_offset(skb, offset,
-                                              (bp->rx_buffers +
-                                               (RX_BUFFER_SIZE * frag)),
-                                              frag_len);
-               offset += RX_BUFFER_SIZE;
-               bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
-               wmb();
-
-               if (frag == last_frag)
-                       break;
-       }
-
-       skb->protocol = eth_type_trans(skb, bp->dev);
-
-       bp->stats.rx_packets++;
-       bp->stats.rx_bytes += len;
-       dev_dbg(&bp->pdev->dev, "received skb of length %u, csum: %08x\n",
-               skb->len, skb->csum);
-       netif_receive_skb(skb);
-
-       return 0;
-}
-
-/* Mark DMA descriptors from begin up to and not including end as unused */
-static void discard_partial_frame(struct macb *bp, unsigned int begin,
-                                 unsigned int end)
-{
-       unsigned int frag;
-
-       for (frag = begin; frag != end; frag = NEXT_RX(frag))
-               bp->rx_ring[frag].addr &= ~MACB_BIT(RX_USED);
-       wmb();
-
-       /*
-        * When this happens, the hardware stats registers for
-        * whatever caused this is updated, so we don't have to record
-        * anything.
-        */
-}
-
-static int macb_rx(struct macb *bp, int budget)
-{
-       int received = 0;
-       unsigned int tail = bp->rx_tail;
-       int first_frag = -1;
-
-       for (; budget > 0; tail = NEXT_RX(tail)) {
-               u32 addr, ctrl;
-
-               rmb();
-               addr = bp->rx_ring[tail].addr;
-               ctrl = bp->rx_ring[tail].ctrl;
-
-               if (!(addr & MACB_BIT(RX_USED)))
-                       break;
-
-               if (ctrl & MACB_BIT(RX_SOF)) {
-                       if (first_frag != -1)
-                               discard_partial_frame(bp, first_frag, tail);
-                       first_frag = tail;
-               }
-
-               if (ctrl & MACB_BIT(RX_EOF)) {
-                       int dropped;
-                       BUG_ON(first_frag == -1);
-
-                       dropped = macb_rx_frame(bp, first_frag, tail);
-                       first_frag = -1;
-                       if (!dropped) {
-                               received++;
-                               budget--;
-                       }
-               }
-       }
-
-       if (first_frag != -1)
-               bp->rx_tail = first_frag;
-       else
-               bp->rx_tail = tail;
-
-       return received;
-}
-
-static int macb_poll(struct napi_struct *napi, int budget)
-{
-       struct macb *bp = container_of(napi, struct macb, napi);
-       int work_done;
-       u32 status;
-
-       status = macb_readl(bp, RSR);
-       macb_writel(bp, RSR, status);
-
-       work_done = 0;
-
-       dev_dbg(&bp->pdev->dev, "poll: status = %08lx, budget = %d\n",
-               (unsigned long)status, budget);
-
-       work_done = macb_rx(bp, budget);
-       if (work_done < budget) {
-               napi_complete(napi);
-
-               /*
-                * We've done what we can to clean the buffers. Make sure we
-                * get notified when new packets arrive.
-                */
-               macb_writel(bp, IER, MACB_RX_INT_FLAGS);
-       }
-
-       /* TODO: Handle errors */
-
-       return work_done;
-}
-
-static irqreturn_t macb_interrupt(int irq, void *dev_id)
-{
-       struct net_device *dev = dev_id;
-       struct macb *bp = netdev_priv(dev);
-       u32 status;
-
-       status = macb_readl(bp, ISR);
-
-       if (unlikely(!status))
-               return IRQ_NONE;
-
-       spin_lock(&bp->lock);
-
-       while (status) {
-               /* close possible race with dev_close */
-               if (unlikely(!netif_running(dev))) {
-                       macb_writel(bp, IDR, ~0UL);
-                       break;
-               }
-
-               if (status & MACB_RX_INT_FLAGS) {
-                       /*
-                        * There's no point taking any more interrupts
-                        * until we have processed the buffers. The
-                        * scheduling call may fail if the poll routine
-                        * is already scheduled, so disable interrupts
-                        * now.
-                        */
-                       macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
-
-                       if (napi_schedule_prep(&bp->napi)) {
-                               dev_dbg(&bp->pdev->dev,
-                                       "scheduling RX softirq\n");
-                               __napi_schedule(&bp->napi);
-                       }
-               }
-
-               if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) |
-                           MACB_BIT(ISR_RLE)))
-                       macb_tx(bp);
-
-               /*
-                * Link change detection isn't possible with RMII, so we'll
-                * add that if/when we get our hands on a full-blown MII PHY.
-                */
-
-               if (status & MACB_BIT(ISR_ROVR)) {
-                       /* We missed at least one packet */
-                       bp->hw_stats.rx_overruns++;
-               }
-
-               if (status & MACB_BIT(HRESP)) {
-                       /*
-                        * TODO: Reset the hardware, and maybe move the printk
-                        * to a lower-priority context as well (work queue?)
-                        */
-                       printk(KERN_ERR "%s: DMA bus error: HRESP not OK\n",
-                              dev->name);
-               }
-
-               status = macb_readl(bp, ISR);
-       }
-
-       spin_unlock(&bp->lock);
-
-       return IRQ_HANDLED;
-}
-
-#ifdef CONFIG_NET_POLL_CONTROLLER
-/*
- * Polling receive - used by netconsole and other diagnostic tools
- * to allow network i/o with interrupts disabled.
- */
-static void macb_poll_controller(struct net_device *dev)
-{
-       unsigned long flags;
-
-       local_irq_save(flags);
-       macb_interrupt(dev->irq, dev);
-       local_irq_restore(flags);
-}
-#endif
-
-static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
-{
-       struct macb *bp = netdev_priv(dev);
-       dma_addr_t mapping;
-       unsigned int len, entry;
-       u32 ctrl;
-       unsigned long flags;
-
-#ifdef DEBUG
-       int i;
-       dev_dbg(&bp->pdev->dev,
-               "start_xmit: len %u head %p data %p tail %p end %p\n",
-               skb->len, skb->head, skb->data,
-               skb_tail_pointer(skb), skb_end_pointer(skb));
-       dev_dbg(&bp->pdev->dev,
-               "data:");
-       for (i = 0; i < 16; i++)
-               printk(" %02x", (unsigned int)skb->data[i]);
-       printk("\n");
-#endif
-
-       len = skb->len;
-       spin_lock_irqsave(&bp->lock, flags);
-
-       /* This is a hard error, log it. */
-       if (TX_BUFFS_AVAIL(bp) < 1) {
-               netif_stop_queue(dev);
-               spin_unlock_irqrestore(&bp->lock, flags);
-               dev_err(&bp->pdev->dev,
-                       "BUG! Tx Ring full when queue awake!\n");
-               dev_dbg(&bp->pdev->dev, "tx_head = %u, tx_tail = %u\n",
-                       bp->tx_head, bp->tx_tail);
-               return NETDEV_TX_BUSY;
-       }
-
-       entry = bp->tx_head;
-       dev_dbg(&bp->pdev->dev, "Allocated ring entry %u\n", entry);
-       mapping = dma_map_single(&bp->pdev->dev, skb->data,
-                                len, DMA_TO_DEVICE);
-       bp->tx_skb[entry].skb = skb;
-       bp->tx_skb[entry].mapping = mapping;
-       dev_dbg(&bp->pdev->dev, "Mapped skb data %p to DMA addr %08lx\n",
-               skb->data, (unsigned long)mapping);
-
-       ctrl = MACB_BF(TX_FRMLEN, len);
-       ctrl |= MACB_BIT(TX_LAST);
-       if (entry == (TX_RING_SIZE - 1))
-               ctrl |= MACB_BIT(TX_WRAP);
-
-       bp->tx_ring[entry].addr = mapping;
-       bp->tx_ring[entry].ctrl = ctrl;
-       wmb();
-
-       entry = NEXT_TX(entry);
-       bp->tx_head = entry;
-
-       skb_tx_timestamp(skb);
-
-       macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
-
-       if (TX_BUFFS_AVAIL(bp) < 1)
-               netif_stop_queue(dev);
-
-       spin_unlock_irqrestore(&bp->lock, flags);
-
-       return NETDEV_TX_OK;
-}
-
-static void macb_free_consistent(struct macb *bp)
-{
-       if (bp->tx_skb) {
-               kfree(bp->tx_skb);
-               bp->tx_skb = NULL;
-       }
-       if (bp->rx_ring) {
-               dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
-                                 bp->rx_ring, bp->rx_ring_dma);
-               bp->rx_ring = NULL;
-       }
-       if (bp->tx_ring) {
-               dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
-                                 bp->tx_ring, bp->tx_ring_dma);
-               bp->tx_ring = NULL;
-       }
-       if (bp->rx_buffers) {
-               dma_free_coherent(&bp->pdev->dev,
-                                 RX_RING_SIZE * RX_BUFFER_SIZE,
-                                 bp->rx_buffers, bp->rx_buffers_dma);
-               bp->rx_buffers = NULL;
-       }
-}
-
-static int macb_alloc_consistent(struct macb *bp)
-{
-       int size;
-
-       size = TX_RING_SIZE * sizeof(struct ring_info);
-       bp->tx_skb = kmalloc(size, GFP_KERNEL);
-       if (!bp->tx_skb)
-               goto out_err;
-
-       size = RX_RING_BYTES;
-       bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
-                                        &bp->rx_ring_dma, GFP_KERNEL);
-       if (!bp->rx_ring)
-               goto out_err;
-       dev_dbg(&bp->pdev->dev,
-               "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
-               size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
-
-       size = TX_RING_BYTES;
-       bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
-                                        &bp->tx_ring_dma, GFP_KERNEL);
-       if (!bp->tx_ring)
-               goto out_err;
-       dev_dbg(&bp->pdev->dev,
-               "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
-               size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
-
-       size = RX_RING_SIZE * RX_BUFFER_SIZE;
-       bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
-                                           &bp->rx_buffers_dma, GFP_KERNEL);
-       if (!bp->rx_buffers)
-               goto out_err;
-       dev_dbg(&bp->pdev->dev,
-               "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
-               size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
-
-       return 0;
-
-out_err:
-       macb_free_consistent(bp);
-       return -ENOMEM;
-}
-
-static void macb_init_rings(struct macb *bp)
-{
-       int i;
-       dma_addr_t addr;
-
-       addr = bp->rx_buffers_dma;
-       for (i = 0; i < RX_RING_SIZE; i++) {
-               bp->rx_ring[i].addr = addr;
-               bp->rx_ring[i].ctrl = 0;
-               addr += RX_BUFFER_SIZE;
-       }
-       bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
-
-       for (i = 0; i < TX_RING_SIZE; i++) {
-               bp->tx_ring[i].addr = 0;
-               bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
-       }
-       bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
-
-       bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
-}
-
-static void macb_reset_hw(struct macb *bp)
-{
-       /* Make sure we have the write buffer for ourselves */
-       wmb();
-
-       /*
-        * Disable RX and TX (XXX: Should we halt the transmission
-        * more gracefully?)
-        */
-       macb_writel(bp, NCR, 0);
-
-       /* Clear the stats registers (XXX: Update stats first?) */
-       macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
-
-       /* Clear all status flags */
-       macb_writel(bp, TSR, ~0UL);
-       macb_writel(bp, RSR, ~0UL);
-
-       /* Disable all interrupts */
-       macb_writel(bp, IDR, ~0UL);
-       macb_readl(bp, ISR);
-}
-
-static void macb_init_hw(struct macb *bp)
-{
-       u32 config;
-
-       macb_reset_hw(bp);
-       __macb_set_hwaddr(bp);
-
-       config = macb_readl(bp, NCFGR) & MACB_BF(CLK, -1L);
-       config |= MACB_BIT(PAE);                /* PAuse Enable */
-       config |= MACB_BIT(DRFCS);              /* Discard Rx FCS */
-       config |= MACB_BIT(BIG);                /* Receive oversized frames */
-       if (bp->dev->flags & IFF_PROMISC)
-               config |= MACB_BIT(CAF);        /* Copy All Frames */
-       if (!(bp->dev->flags & IFF_BROADCAST))
-               config |= MACB_BIT(NBC);        /* No BroadCast */
-       macb_writel(bp, NCFGR, config);
-
-       /* Initialize TX and RX buffers */
-       macb_writel(bp, RBQP, bp->rx_ring_dma);
-       macb_writel(bp, TBQP, bp->tx_ring_dma);
-
-       /* Enable TX and RX */
-       macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
-
-       /* Enable interrupts */
-       macb_writel(bp, IER, (MACB_BIT(RCOMP)
-                             | MACB_BIT(RXUBR)
-                             | MACB_BIT(ISR_TUND)
-                             | MACB_BIT(ISR_RLE)
-                             | MACB_BIT(TXERR)
-                             | MACB_BIT(TCOMP)
-                             | MACB_BIT(ISR_ROVR)
-                             | MACB_BIT(HRESP)));
-
-}
-
-/*
- * The hash address register is 64 bits long and takes up two
- * locations in the memory map.  The least significant bits are stored
- * in EMAC_HSL and the most significant bits in EMAC_HSH.
- *
- * The unicast hash enable and the multicast hash enable bits in the
- * network configuration register enable the reception of hash matched
- * frames. The destination address is reduced to a 6 bit index into
- * the 64 bit hash register using the following hash function.  The
- * hash function is an exclusive or of every sixth bit of the
- * destination address.
- *
- * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
- * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
- * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
- * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
- * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
- * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
- *
- * da[0] represents the least significant bit of the first byte
- * received, that is, the multicast/unicast indicator, and da[47]
- * represents the most significant bit of the last byte received.  If
- * the hash index, hi[n], points to a bit that is set in the hash
- * register then the frame will be matched according to whether the
- * frame is multicast or unicast.  A multicast match will be signalled
- * if the multicast hash enable bit is set, da[0] is 1 and the hash
- * index points to a bit set in the hash register.  A unicast match
- * will be signalled if the unicast hash enable bit is set, da[0] is 0
- * and the hash index points to a bit set in the hash register.  To
- * receive all multicast frames, the hash register should be set with
- * all ones and the multicast hash enable bit should be set in the
- * network configuration register.
- */
-
-static inline int hash_bit_value(int bitnr, __u8 *addr)
-{
-       if (addr[bitnr / 8] & (1 << (bitnr % 8)))
-               return 1;
-       return 0;
-}
-
-/*
- * Return the hash index value for the specified address.
- */
-static int hash_get_index(__u8 *addr)
-{
-       int i, j, bitval;
-       int hash_index = 0;
-
-       for (j = 0; j < 6; j++) {
-               for (i = 0, bitval = 0; i < 8; i++)
-                       bitval ^= hash_bit_value(i*6 + j, addr);
-
-               hash_index |= (bitval << j);
-       }
-
-       return hash_index;
-}
-
-/*
- * Add multicast addresses to the internal multicast-hash table.
- */
-static void macb_sethashtable(struct net_device *dev)
-{
-       struct netdev_hw_addr *ha;
-       unsigned long mc_filter[2];
-       unsigned int bitnr;
-       struct macb *bp = netdev_priv(dev);
-
-       mc_filter[0] = mc_filter[1] = 0;
-
-       netdev_for_each_mc_addr(ha, dev) {
-               bitnr = hash_get_index(ha->addr);
-               mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
-       }
-
-       macb_writel(bp, HRB, mc_filter[0]);
-       macb_writel(bp, HRT, mc_filter[1]);
-}
-
-/*
- * Enable/Disable promiscuous and multicast modes.
- */
-static void macb_set_rx_mode(struct net_device *dev)
-{
-       unsigned long cfg;
-       struct macb *bp = netdev_priv(dev);
-
-       cfg = macb_readl(bp, NCFGR);
-
-       if (dev->flags & IFF_PROMISC)
-               /* Enable promiscuous mode */
-               cfg |= MACB_BIT(CAF);
-       else if (dev->flags & (~IFF_PROMISC))
-                /* Disable promiscuous mode */
-               cfg &= ~MACB_BIT(CAF);
-
-       if (dev->flags & IFF_ALLMULTI) {
-               /* Enable all multicast mode */
-               macb_writel(bp, HRB, -1);
-               macb_writel(bp, HRT, -1);
-               cfg |= MACB_BIT(NCFGR_MTI);
-       } else if (!netdev_mc_empty(dev)) {
-               /* Enable specific multicasts */
-               macb_sethashtable(dev);
-               cfg |= MACB_BIT(NCFGR_MTI);
-       } else if (dev->flags & (~IFF_ALLMULTI)) {
-               /* Disable all multicast mode */
-               macb_writel(bp, HRB, 0);
-               macb_writel(bp, HRT, 0);
-               cfg &= ~MACB_BIT(NCFGR_MTI);
-       }
-
-       macb_writel(bp, NCFGR, cfg);
-}
-
-static int macb_open(struct net_device *dev)
-{
-       struct macb *bp = netdev_priv(dev);
-       int err;
-
-       dev_dbg(&bp->pdev->dev, "open\n");
-
-       /* if the phy is not yet register, retry later*/
-       if (!bp->phy_dev)
-               return -EAGAIN;
-
-       if (!is_valid_ether_addr(dev->dev_addr))
-               return -EADDRNOTAVAIL;
-
-       err = macb_alloc_consistent(bp);
-       if (err) {
-               printk(KERN_ERR
-                      "%s: Unable to allocate DMA memory (error %d)\n",
-                      dev->name, err);
-               return err;
-       }
-
-       napi_enable(&bp->napi);
-
-       macb_init_rings(bp);
-       macb_init_hw(bp);
-
-       /* schedule a link state check */
-       phy_start(bp->phy_dev);
-
-       netif_start_queue(dev);
-
-       return 0;
-}
-
-static int macb_close(struct net_device *dev)
-{
-       struct macb *bp = netdev_priv(dev);
-       unsigned long flags;
-
-       netif_stop_queue(dev);
-       napi_disable(&bp->napi);
-
-       if (bp->phy_dev)
-               phy_stop(bp->phy_dev);
-
-       spin_lock_irqsave(&bp->lock, flags);
-       macb_reset_hw(bp);
-       netif_carrier_off(dev);
-       spin_unlock_irqrestore(&bp->lock, flags);
-
-       macb_free_consistent(bp);
-
-       return 0;
-}
-
-static struct net_device_stats *macb_get_stats(struct net_device *dev)
-{
-       struct macb *bp = netdev_priv(dev);
-       struct net_device_stats *nstat = &bp->stats;
-       struct macb_stats *hwstat = &bp->hw_stats;
-
-       /* read stats from hardware */
-       macb_update_stats(bp);
-
-       /* Convert HW stats into netdevice stats */
-       nstat->rx_errors = (hwstat->rx_fcs_errors +
-                           hwstat->rx_align_errors +
-                           hwstat->rx_resource_errors +
-                           hwstat->rx_overruns +
-                           hwstat->rx_oversize_pkts +
-                           hwstat->rx_jabbers +
-                           hwstat->rx_undersize_pkts +
-                           hwstat->sqe_test_errors +
-                           hwstat->rx_length_mismatch);
-       nstat->tx_errors = (hwstat->tx_late_cols +
-                           hwstat->tx_excessive_cols +
-                           hwstat->tx_underruns +
-                           hwstat->tx_carrier_errors);
-       nstat->collisions = (hwstat->tx_single_cols +
-                            hwstat->tx_multiple_cols +
-                            hwstat->tx_excessive_cols);
-       nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
-                                  hwstat->rx_jabbers +
-                                  hwstat->rx_undersize_pkts +
-                                  hwstat->rx_length_mismatch);
-       nstat->rx_over_errors = hwstat->rx_resource_errors +
-                                  hwstat->rx_overruns;
-       nstat->rx_crc_errors = hwstat->rx_fcs_errors;
-       nstat->rx_frame_errors = hwstat->rx_align_errors;
-       nstat->rx_fifo_errors = hwstat->rx_overruns;
-       /* XXX: What does "missed" mean? */
-       nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
-       nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
-       nstat->tx_fifo_errors = hwstat->tx_underruns;
-       /* Don't know about heartbeat or window errors... */
-
-       return nstat;
-}
-
-static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
-       struct macb *bp = netdev_priv(dev);
-       struct phy_device *phydev = bp->phy_dev;
-
-       if (!phydev)
-               return -ENODEV;
-
-       return phy_ethtool_gset(phydev, cmd);
-}
-
-static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
-{
-       struct macb *bp = netdev_priv(dev);
-       struct phy_device *phydev = bp->phy_dev;
-
-       if (!phydev)
-               return -ENODEV;
-
-       return phy_ethtool_sset(phydev, cmd);
-}
-
-static void macb_get_drvinfo(struct net_device *dev,
-                            struct ethtool_drvinfo *info)
-{
-       struct macb *bp = netdev_priv(dev);
-
-       strcpy(info->driver, bp->pdev->dev.driver->name);
-       strcpy(info->version, "$Revision: 1.14 $");
-       strcpy(info->bus_info, dev_name(&bp->pdev->dev));
-}
-
-static const struct ethtool_ops macb_ethtool_ops = {
-       .get_settings           = macb_get_settings,
-       .set_settings           = macb_set_settings,
-       .get_drvinfo            = macb_get_drvinfo,
-       .get_link               = ethtool_op_get_link,
-};
-
-static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-{
-       struct macb *bp = netdev_priv(dev);
-       struct phy_device *phydev = bp->phy_dev;
-
-       if (!netif_running(dev))
-               return -EINVAL;
-
-       if (!phydev)
-               return -ENODEV;
-
-       return phy_mii_ioctl(phydev, rq, cmd);
-}
-
-static const struct net_device_ops macb_netdev_ops = {
-       .ndo_open               = macb_open,
-       .ndo_stop               = macb_close,
-       .ndo_start_xmit         = macb_start_xmit,
-       .ndo_set_multicast_list = macb_set_rx_mode,
-       .ndo_get_stats          = macb_get_stats,
-       .ndo_do_ioctl           = macb_ioctl,
-       .ndo_validate_addr      = eth_validate_addr,
-       .ndo_change_mtu         = eth_change_mtu,
-       .ndo_set_mac_address    = eth_mac_addr,
-#ifdef CONFIG_NET_POLL_CONTROLLER
-       .ndo_poll_controller    = macb_poll_controller,
-#endif
-};
-
-static int __init macb_probe(struct platform_device *pdev)
-{
-       struct eth_platform_data *pdata;
-       struct resource *regs;
-       struct net_device *dev;
-       struct macb *bp;
-       struct phy_device *phydev;
-       unsigned long pclk_hz;
-       u32 config;
-       int err = -ENXIO;
-
-       regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       if (!regs) {
-               dev_err(&pdev->dev, "no mmio resource defined\n");
-               goto err_out;
-       }
-
-       err = -ENOMEM;
-       dev = alloc_etherdev(sizeof(*bp));
-       if (!dev) {
-               dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n");
-               goto err_out;
-       }
-
-       SET_NETDEV_DEV(dev, &pdev->dev);
-
-       /* TODO: Actually, we have some interesting features... */
-       dev->features |= 0;
-
-       bp = netdev_priv(dev);
-       bp->pdev = pdev;
-       bp->dev = dev;
-
-       spin_lock_init(&bp->lock);
-
-#if defined(CONFIG_ARCH_AT91)
-       bp->pclk = clk_get(&pdev->dev, "macb_clk");
-       if (IS_ERR(bp->pclk)) {
-               dev_err(&pdev->dev, "failed to get macb_clk\n");
-               goto err_out_free_dev;
-       }
-       clk_enable(bp->pclk);
-#else
-       bp->pclk = clk_get(&pdev->dev, "pclk");
-       if (IS_ERR(bp->pclk)) {
-               dev_err(&pdev->dev, "failed to get pclk\n");
-               goto err_out_free_dev;
-       }
-       bp->hclk = clk_get(&pdev->dev, "hclk");
-       if (IS_ERR(bp->hclk)) {
-               dev_err(&pdev->dev, "failed to get hclk\n");
-               goto err_out_put_pclk;
-       }
-
-       clk_enable(bp->pclk);
-       clk_enable(bp->hclk);
-#endif
-
-       bp->regs = ioremap(regs->start, resource_size(regs));
-       if (!bp->regs) {
-               dev_err(&pdev->dev, "failed to map registers, aborting.\n");
-               err = -ENOMEM;
-               goto err_out_disable_clocks;
-       }
-
-       dev->irq = platform_get_irq(pdev, 0);
-       err = request_irq(dev->irq, macb_interrupt, 0, dev->name, dev);
-       if (err) {
-               printk(KERN_ERR
-                      "%s: Unable to request IRQ %d (error %d)\n",
-                      dev->name, dev->irq, err);
-               goto err_out_iounmap;
-       }
-
-       dev->netdev_ops = &macb_netdev_ops;
-       netif_napi_add(dev, &bp->napi, macb_poll, 64);
-       dev->ethtool_ops = &macb_ethtool_ops;
-
-       dev->base_addr = regs->start;
-
-       /* Set MII management clock divider */
-       pclk_hz = clk_get_rate(bp->pclk);
-       if (pclk_hz <= 20000000)
-               config = MACB_BF(CLK, MACB_CLK_DIV8);
-       else if (pclk_hz <= 40000000)
-               config = MACB_BF(CLK, MACB_CLK_DIV16);
-       else if (pclk_hz <= 80000000)
-               config = MACB_BF(CLK, MACB_CLK_DIV32);
-       else
-               config = MACB_BF(CLK, MACB_CLK_DIV64);
-       macb_writel(bp, NCFGR, config);
-
-       macb_get_hwaddr(bp);
-       pdata = pdev->dev.platform_data;
-
-       if (pdata && pdata->is_rmii)
-#if defined(CONFIG_ARCH_AT91)
-               macb_writel(bp, USRIO, (MACB_BIT(RMII) | MACB_BIT(CLKEN)) );
-#else
-               macb_writel(bp, USRIO, 0);
-#endif
-       else
-#if defined(CONFIG_ARCH_AT91)
-               macb_writel(bp, USRIO, MACB_BIT(CLKEN));
-#else
-               macb_writel(bp, USRIO, MACB_BIT(MII));
-#endif
-
-       bp->tx_pending = DEF_TX_RING_PENDING;
-
-       err = register_netdev(dev);
-       if (err) {
-               dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
-               goto err_out_free_irq;
-       }
-
-       if (macb_mii_init(bp) != 0) {
-               goto err_out_unregister_netdev;
-       }
-
-       platform_set_drvdata(pdev, dev);
-
-       printk(KERN_INFO "%s: Atmel MACB at 0x%08lx irq %d (%pM)\n",
-              dev->name, dev->base_addr, dev->irq, dev->dev_addr);
-
-       phydev = bp->phy_dev;
-       printk(KERN_INFO "%s: attached PHY driver [%s] "
-               "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
-               phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
-
-       return 0;
-
-err_out_unregister_netdev:
-       unregister_netdev(dev);
-err_out_free_irq:
-       free_irq(dev->irq, dev);
-err_out_iounmap:
-       iounmap(bp->regs);
-err_out_disable_clocks:
-#ifndef CONFIG_ARCH_AT91
-       clk_disable(bp->hclk);
-       clk_put(bp->hclk);
-#endif
-       clk_disable(bp->pclk);
-#ifndef CONFIG_ARCH_AT91
-err_out_put_pclk:
-#endif
-       clk_put(bp->pclk);
-err_out_free_dev:
-       free_netdev(dev);
-err_out:
-       platform_set_drvdata(pdev, NULL);
-       return err;
-}
-
-static int __exit macb_remove(struct platform_device *pdev)
-{
-       struct net_device *dev;
-       struct macb *bp;
-
-       dev = platform_get_drvdata(pdev);
-
-       if (dev) {
-               bp = netdev_priv(dev);
-               if (bp->phy_dev)
-                       phy_disconnect(bp->phy_dev);
-               mdiobus_unregister(bp->mii_bus);
-               kfree(bp->mii_bus->irq);
-               mdiobus_free(bp->mii_bus);
-               unregister_netdev(dev);
-               free_irq(dev->irq, dev);
-               iounmap(bp->regs);
-#ifndef CONFIG_ARCH_AT91
-               clk_disable(bp->hclk);
-               clk_put(bp->hclk);
-#endif
-               clk_disable(bp->pclk);
-               clk_put(bp->pclk);
-               free_netdev(dev);
-               platform_set_drvdata(pdev, NULL);
-       }
-
-       return 0;
-}
-
-#ifdef CONFIG_PM
-static int macb_suspend(struct platform_device *pdev, pm_message_t state)
-{
-       struct net_device *netdev = platform_get_drvdata(pdev);
-       struct macb *bp = netdev_priv(netdev);
-
-       netif_device_detach(netdev);
-
-#ifndef CONFIG_ARCH_AT91
-       clk_disable(bp->hclk);
-#endif
-       clk_disable(bp->pclk);
-
-       return 0;
-}
-
-static int macb_resume(struct platform_device *pdev)
-{
-       struct net_device *netdev = platform_get_drvdata(pdev);
-       struct macb *bp = netdev_priv(netdev);
-
-       clk_enable(bp->pclk);
-#ifndef CONFIG_ARCH_AT91
-       clk_enable(bp->hclk);
-#endif
-
-       netif_device_attach(netdev);
-
-       return 0;
-}
-#else
-#define macb_suspend   NULL
-#define macb_resume    NULL
-#endif
-
-static struct platform_driver macb_driver = {
-       .remove         = __exit_p(macb_remove),
-       .suspend        = macb_suspend,
-       .resume         = macb_resume,
-       .driver         = {
-               .name           = "macb",
-               .owner  = THIS_MODULE,
-       },
-};
-
-static int __init macb_init(void)
-{
-       return platform_driver_probe(&macb_driver, macb_probe);
-}
-
-static void __exit macb_exit(void)
-{
-       platform_driver_unregister(&macb_driver);
-}
-
-module_init(macb_init);
-module_exit(macb_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Atmel MACB Ethernet driver");
-MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
-MODULE_ALIAS("platform:macb");
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
deleted file mode 100644 (file)
index d3212f6..0000000
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Atmel MACB Ethernet Controller driver
- *
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef _MACB_H
-#define _MACB_H
-
-/* MACB register offsets */
-#define MACB_NCR                               0x0000
-#define MACB_NCFGR                             0x0004
-#define MACB_NSR                               0x0008
-#define MACB_TSR                               0x0014
-#define MACB_RBQP                              0x0018
-#define MACB_TBQP                              0x001c
-#define MACB_RSR                               0x0020
-#define MACB_ISR                               0x0024
-#define MACB_IER                               0x0028
-#define MACB_IDR                               0x002c
-#define MACB_IMR                               0x0030
-#define MACB_MAN                               0x0034
-#define MACB_PTR                               0x0038
-#define MACB_PFR                               0x003c
-#define MACB_FTO                               0x0040
-#define MACB_SCF                               0x0044
-#define MACB_MCF                               0x0048
-#define MACB_FRO                               0x004c
-#define MACB_FCSE                              0x0050
-#define MACB_ALE                               0x0054
-#define MACB_DTF                               0x0058
-#define MACB_LCOL                              0x005c
-#define MACB_EXCOL                             0x0060
-#define MACB_TUND                              0x0064
-#define MACB_CSE                               0x0068
-#define MACB_RRE                               0x006c
-#define MACB_ROVR                              0x0070
-#define MACB_RSE                               0x0074
-#define MACB_ELE                               0x0078
-#define MACB_RJA                               0x007c
-#define MACB_USF                               0x0080
-#define MACB_STE                               0x0084
-#define MACB_RLE                               0x0088
-#define MACB_TPF                               0x008c
-#define MACB_HRB                               0x0090
-#define MACB_HRT                               0x0094
-#define MACB_SA1B                              0x0098
-#define MACB_SA1T                              0x009c
-#define MACB_SA2B                              0x00a0
-#define MACB_SA2T                              0x00a4
-#define MACB_SA3B                              0x00a8
-#define MACB_SA3T                              0x00ac
-#define MACB_SA4B                              0x00b0
-#define MACB_SA4T                              0x00b4
-#define MACB_TID                               0x00b8
-#define MACB_TPQ                               0x00bc
-#define MACB_USRIO                             0x00c0
-#define MACB_WOL                               0x00c4
-
-/* Bitfields in NCR */
-#define MACB_LB_OFFSET                         0
-#define MACB_LB_SIZE                           1
-#define MACB_LLB_OFFSET                                1
-#define MACB_LLB_SIZE                          1
-#define MACB_RE_OFFSET                         2
-#define MACB_RE_SIZE                           1
-#define MACB_TE_OFFSET                         3
-#define MACB_TE_SIZE                           1
-#define MACB_MPE_OFFSET                                4
-#define MACB_MPE_SIZE                          1
-#define MACB_CLRSTAT_OFFSET                    5
-#define MACB_CLRSTAT_SIZE                      1
-#define MACB_INCSTAT_OFFSET                    6
-#define MACB_INCSTAT_SIZE                      1
-#define MACB_WESTAT_OFFSET                     7
-#define MACB_WESTAT_SIZE                       1
-#define MACB_BP_OFFSET                         8
-#define MACB_BP_SIZE                           1
-#define MACB_TSTART_OFFSET                     9
-#define MACB_TSTART_SIZE                       1
-#define MACB_THALT_OFFSET                      10
-#define MACB_THALT_SIZE                                1
-#define MACB_NCR_TPF_OFFSET                    11
-#define MACB_NCR_TPF_SIZE                      1
-#define MACB_TZQ_OFFSET                                12
-#define MACB_TZQ_SIZE                          1
-
-/* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET                                0
-#define MACB_SPD_SIZE                          1
-#define MACB_FD_OFFSET                         1
-#define MACB_FD_SIZE                           1
-#define MACB_BIT_RATE_OFFSET                   2
-#define MACB_BIT_RATE_SIZE                     1
-#define MACB_JFRAME_OFFSET                     3
-#define MACB_JFRAME_SIZE                       1
-#define MACB_CAF_OFFSET                                4
-#define MACB_CAF_SIZE                          1
-#define MACB_NBC_OFFSET                                5
-#define MACB_NBC_SIZE                          1
-#define MACB_NCFGR_MTI_OFFSET                  6
-#define MACB_NCFGR_MTI_SIZE                    1
-#define MACB_UNI_OFFSET                                7
-#define MACB_UNI_SIZE                          1
-#define MACB_BIG_OFFSET                                8
-#define MACB_BIG_SIZE                          1
-#define MACB_EAE_OFFSET                                9
-#define MACB_EAE_SIZE                          1
-#define MACB_CLK_OFFSET                                10
-#define MACB_CLK_SIZE                          2
-#define MACB_RTY_OFFSET                                12
-#define MACB_RTY_SIZE                          1
-#define MACB_PAE_OFFSET                                13
-#define MACB_PAE_SIZE                          1
-#define MACB_RBOF_OFFSET                       14
-#define MACB_RBOF_SIZE                         2
-#define MACB_RLCE_OFFSET                       16
-#define MACB_RLCE_SIZE                         1
-#define MACB_DRFCS_OFFSET                      17
-#define MACB_DRFCS_SIZE                                1
-#define MACB_EFRHD_OFFSET                      18
-#define MACB_EFRHD_SIZE                                1
-#define MACB_IRXFCS_OFFSET                     19
-#define MACB_IRXFCS_SIZE                       1
-
-/* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET                   0
-#define MACB_NSR_LINK_SIZE                     1
-#define MACB_MDIO_OFFSET                       1
-#define MACB_MDIO_SIZE                         1
-#define MACB_IDLE_OFFSET                       2
-#define MACB_IDLE_SIZE                         1
-
-/* Bitfields in TSR */
-#define MACB_UBR_OFFSET                                0
-#define MACB_UBR_SIZE                          1
-#define MACB_COL_OFFSET                                1
-#define MACB_COL_SIZE                          1
-#define MACB_TSR_RLE_OFFSET                    2
-#define MACB_TSR_RLE_SIZE                      1
-#define MACB_TGO_OFFSET                                3
-#define MACB_TGO_SIZE                          1
-#define MACB_BEX_OFFSET                                4
-#define MACB_BEX_SIZE                          1
-#define MACB_COMP_OFFSET                       5
-#define MACB_COMP_SIZE                         1
-#define MACB_UND_OFFSET                                6
-#define MACB_UND_SIZE                          1
-
-/* Bitfields in RSR */
-#define MACB_BNA_OFFSET                                0
-#define MACB_BNA_SIZE                          1
-#define MACB_REC_OFFSET                                1
-#define MACB_REC_SIZE                          1
-#define MACB_OVR_OFFSET                                2
-#define MACB_OVR_SIZE                          1
-
-/* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET                                0
-#define MACB_MFD_SIZE                          1
-#define MACB_RCOMP_OFFSET                      1
-#define MACB_RCOMP_SIZE                                1
-#define MACB_RXUBR_OFFSET                      2
-#define MACB_RXUBR_SIZE                                1
-#define MACB_TXUBR_OFFSET                      3
-#define MACB_TXUBR_SIZE                                1
-#define MACB_ISR_TUND_OFFSET                   4
-#define MACB_ISR_TUND_SIZE                     1
-#define MACB_ISR_RLE_OFFSET                    5
-#define MACB_ISR_RLE_SIZE                      1
-#define MACB_TXERR_OFFSET                      6
-#define MACB_TXERR_SIZE                                1
-#define MACB_TCOMP_OFFSET                      7
-#define MACB_TCOMP_SIZE                                1
-#define MACB_ISR_LINK_OFFSET                   9
-#define MACB_ISR_LINK_SIZE                     1
-#define MACB_ISR_ROVR_OFFSET                   10
-#define MACB_ISR_ROVR_SIZE                     1
-#define MACB_HRESP_OFFSET                      11
-#define MACB_HRESP_SIZE                                1
-#define MACB_PFR_OFFSET                                12
-#define MACB_PFR_SIZE                          1
-#define MACB_PTZ_OFFSET                                13
-#define MACB_PTZ_SIZE                          1
-
-/* Bitfields in MAN */
-#define MACB_DATA_OFFSET                       0
-#define MACB_DATA_SIZE                         16
-#define MACB_CODE_OFFSET                       16
-#define MACB_CODE_SIZE                         2
-#define MACB_REGA_OFFSET                       18
-#define MACB_REGA_SIZE                         5
-#define MACB_PHYA_OFFSET                       23
-#define MACB_PHYA_SIZE                         5
-#define MACB_RW_OFFSET                         28
-#define MACB_RW_SIZE                           2
-#define MACB_SOF_OFFSET                                30
-#define MACB_SOF_SIZE                          2
-
-/* Bitfields in USRIO (AVR32) */
-#define MACB_MII_OFFSET                                0
-#define MACB_MII_SIZE                          1
-#define MACB_EAM_OFFSET                                1
-#define MACB_EAM_SIZE                          1
-#define MACB_TX_PAUSE_OFFSET                   2
-#define MACB_TX_PAUSE_SIZE                     1
-#define MACB_TX_PAUSE_ZERO_OFFSET              3
-#define MACB_TX_PAUSE_ZERO_SIZE                        1
-
-/* Bitfields in USRIO (AT91) */
-#define MACB_RMII_OFFSET                       0
-#define MACB_RMII_SIZE                         1
-#define MACB_CLKEN_OFFSET                      1
-#define MACB_CLKEN_SIZE                                1
-
-/* Bitfields in WOL */
-#define MACB_IP_OFFSET                         0
-#define MACB_IP_SIZE                           16
-#define MACB_MAG_OFFSET                                16
-#define MACB_MAG_SIZE                          1
-#define MACB_ARP_OFFSET                                17
-#define MACB_ARP_SIZE                          1
-#define MACB_SA1_OFFSET                                18
-#define MACB_SA1_SIZE                          1
-#define MACB_WOL_MTI_OFFSET                    19
-#define MACB_WOL_MTI_SIZE                      1
-
-/* Constants for CLK */
-#define MACB_CLK_DIV8                          0
-#define MACB_CLK_DIV16                         1
-#define MACB_CLK_DIV32                         2
-#define MACB_CLK_DIV64                         3
-
-/* Constants for MAN register */
-#define MACB_MAN_SOF                           1
-#define MACB_MAN_WRITE                         1
-#define MACB_MAN_READ                          2
-#define MACB_MAN_CODE                          2
-
-/* Bit manipulation macros */
-#define MACB_BIT(name)                                 \
-       (1 << MACB_##name##_OFFSET)
-#define MACB_BF(name,value)                            \
-       (((value) & ((1 << MACB_##name##_SIZE) - 1))    \
-        << MACB_##name##_OFFSET)
-#define MACB_BFEXT(name,value)\
-       (((value) >> MACB_##name##_OFFSET)              \
-        & ((1 << MACB_##name##_SIZE) - 1))
-#define MACB_BFINS(name,value,old)                     \
-       (((old) & ~(((1 << MACB_##name##_SIZE) - 1)     \
-                   << MACB_##name##_OFFSET))           \
-        | MACB_BF(name,value))
-
-/* Register access macros */
-#define macb_readl(port,reg)                           \
-       __raw_readl((port)->regs + MACB_##reg)
-#define macb_writel(port,reg,value)                    \
-       __raw_writel((value), (port)->regs + MACB_##reg)
-
-struct dma_desc {
-       u32     addr;
-       u32     ctrl;
-};
-
-/* DMA descriptor bitfields */
-#define MACB_RX_USED_OFFSET                    0
-#define MACB_RX_USED_SIZE                      1
-#define MACB_RX_WRAP_OFFSET                    1
-#define MACB_RX_WRAP_SIZE                      1
-#define MACB_RX_WADDR_OFFSET                   2
-#define MACB_RX_WADDR_SIZE                     30
-
-#define MACB_RX_FRMLEN_OFFSET                  0
-#define MACB_RX_FRMLEN_SIZE                    12
-#define MACB_RX_OFFSET_OFFSET                  12
-#define MACB_RX_OFFSET_SIZE                    2
-#define MACB_RX_SOF_OFFSET                     14
-#define MACB_RX_SOF_SIZE                       1
-#define MACB_RX_EOF_OFFSET                     15
-#define MACB_RX_EOF_SIZE                       1
-#define MACB_RX_CFI_OFFSET                     16
-#define MACB_RX_CFI_SIZE                       1
-#define MACB_RX_VLAN_PRI_OFFSET                        17
-#define MACB_RX_VLAN_PRI_SIZE                  3
-#define MACB_RX_PRI_TAG_OFFSET                 20
-#define MACB_RX_PRI_TAG_SIZE                   1
-#define MACB_RX_VLAN_TAG_OFFSET                        21
-#define MACB_RX_VLAN_TAG_SIZE                  1
-#define MACB_RX_TYPEID_MATCH_OFFSET            22
-#define MACB_RX_TYPEID_MATCH_SIZE              1
-#define MACB_RX_SA4_MATCH_OFFSET               23
-#define MACB_RX_SA4_MATCH_SIZE                 1
-#define MACB_RX_SA3_MATCH_OFFSET               24
-#define MACB_RX_SA3_MATCH_SIZE                 1
-#define MACB_RX_SA2_MATCH_OFFSET               25
-#define MACB_RX_SA2_MATCH_SIZE                 1
-#define MACB_RX_SA1_MATCH_OFFSET               26
-#define MACB_RX_SA1_MATCH_SIZE                 1
-#define MACB_RX_EXT_MATCH_OFFSET               28
-#define MACB_RX_EXT_MATCH_SIZE                 1
-#define MACB_RX_UHASH_MATCH_OFFSET             29
-#define MACB_RX_UHASH_MATCH_SIZE               1
-#define MACB_RX_MHASH_MATCH_OFFSET             30
-#define MACB_RX_MHASH_MATCH_SIZE               1
-#define MACB_RX_BROADCAST_OFFSET               31
-#define MACB_RX_BROADCAST_SIZE                 1
-
-#define MACB_TX_FRMLEN_OFFSET                  0
-#define MACB_TX_FRMLEN_SIZE                    11
-#define MACB_TX_LAST_OFFSET                    15
-#define MACB_TX_LAST_SIZE                      1
-#define MACB_TX_NOCRC_OFFSET                   16
-#define MACB_TX_NOCRC_SIZE                     1
-#define MACB_TX_BUF_EXHAUSTED_OFFSET           27
-#define MACB_TX_BUF_EXHAUSTED_SIZE             1
-#define MACB_TX_UNDERRUN_OFFSET                        28
-#define MACB_TX_UNDERRUN_SIZE                  1
-#define MACB_TX_ERROR_OFFSET                   29
-#define MACB_TX_ERROR_SIZE                     1
-#define MACB_TX_WRAP_OFFSET                    30
-#define MACB_TX_WRAP_SIZE                      1
-#define MACB_TX_USED_OFFSET                    31
-#define MACB_TX_USED_SIZE                      1
-
-struct ring_info {
-       struct sk_buff          *skb;
-       dma_addr_t              mapping;
-};
-
-/*
- * Hardware-collected statistics. Used when updating the network
- * device stats by a periodic timer.
- */
-struct macb_stats {
-       u32     rx_pause_frames;
-       u32     tx_ok;
-       u32     tx_single_cols;
-       u32     tx_multiple_cols;
-       u32     rx_ok;
-       u32     rx_fcs_errors;
-       u32     rx_align_errors;
-       u32     tx_deferred;
-       u32     tx_late_cols;
-       u32     tx_excessive_cols;
-       u32     tx_underruns;
-       u32     tx_carrier_errors;
-       u32     rx_resource_errors;
-       u32     rx_overruns;
-       u32     rx_symbol_errors;
-       u32     rx_oversize_pkts;
-       u32     rx_jabbers;
-       u32     rx_undersize_pkts;
-       u32     sqe_test_errors;
-       u32     rx_length_mismatch;
-       u32     tx_pause_frames;
-};
-
-struct macb {
-       void __iomem            *regs;
-
-       unsigned int            rx_tail;
-       struct dma_desc         *rx_ring;
-       void                    *rx_buffers;
-
-       unsigned int            tx_head, tx_tail;
-       struct dma_desc         *tx_ring;
-       struct ring_info        *tx_skb;
-
-       spinlock_t              lock;
-       struct platform_device  *pdev;
-       struct clk              *pclk;
-       struct clk              *hclk;
-       struct net_device       *dev;
-       struct napi_struct      napi;
-       struct net_device_stats stats;
-       struct macb_stats       hw_stats;
-
-       dma_addr_t              rx_ring_dma;
-       dma_addr_t              tx_ring_dma;
-       dma_addr_t              rx_buffers_dma;
-
-       unsigned int            rx_pending, tx_pending;
-
-       struct mii_bus          *mii_bus;
-       struct phy_device       *phy_dev;
-       unsigned int            link;
-       unsigned int            speed;
-       unsigned int            duplex;
-};
-
-#endif /* _MACB_H */