ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand

LLVM's integrated assembler does not accept r15 as mrc operand.
  arch/arm/boot/compressed/head.S:1267:16: error: operand must be a register in range [r0, r14] or apsr_nzcv
  1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
                 ^

Use APSR_nzcv instead of r15. The GNU assembler supports this
syntax since binutils 2.21 [0].

[0] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=db472d6ff0f438a21b357249a9b48e4b74498076

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 93dffed0ac6e02b476ad82773f56727bf9118c80..ae70754d003daab563cf07e16e8fb9713e645023 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -1273,7 +1273,7 @@ iflush:
 __armv5tej_mmu_cache_flush:
                tst     r4, #1
                movne   pc, lr
-1:             mrc     p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
+1:             mrc     p15, 0, APSR_nzcv, c7, c14, 3   @ test,clean,invalidate D cache
                bne     1b
                mcr     p15, 0, r0, c7, c5, 0   @ flush I cache
                mcr     p15, 0, r0, c7, c10, 4  @ drain WB

diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index ac5afde12f35cfe09eccd8fa449f0ae4b7057962..e927187157d7d577e0bff82d872ca7758ec23532 100644 (file)
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -138,7 +138,7 @@ ENTRY(arm1026_flush_kern_cache_all)
        mov     ip, #0
 __flush_whole_cache:
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-1:     mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
+1:     mrc     p15, 0, APSR_nzcv, c7, c14, 3           @ test, clean, invalidate
        bne     1b
 #endif
        tst     r2, #VM_EXEC
@@ -363,7 +363,7 @@ ENTRY(cpu_arm1026_switch_mm)
 #ifdef CONFIG_MMU
        mov     r1, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
-1:     mrc     p15, 0, r15, c7, c14, 3         @ test, clean, invalidate
+1:     mrc     p15, 0, APSR_nzcv, c7, c14, 3           @ test, clean, invalidate
        bne     1b
 #endif
 #ifndef CONFIG_CPU_ICACHE_DISABLE

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index f3cd08f353f00a92e186a075ee7ab17ec41f65a1..4ef89e1d11276ea9f944cd9705f58de12edb6b21 100644 (file)
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -131,7 +131,7 @@ __flush_whole_cache:
 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
 #else
-1:     mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
+1:     mrc     p15, 0, APSR_nzcv, c7, c14, 3   @ test,clean,invalidate
        bne     1b
 #endif
        tst     r2, #VM_EXEC
@@ -358,7 +358,7 @@ ENTRY(cpu_arm926_switch_mm)
        mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
 #else
 @ && 'Clean & Invalidate whole DCache'
-1:     mrc     p15, 0, r15, c7, c14, 3         @ test,clean,invalidate
+1:     mrc     p15, 0, APSR_nzcv, c7, c14, 3   @ test,clean,invalidate
        bne     1b
 #endif
        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache