drm/amd/display: skip dsc config for navi10 bring up

[why] we meet a bug when program dsc register even dsc mode is not
enabled. disable dsc config for now. we will re-visit this issue.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 724b5a9e47d0d80d23c5eed364de7ceaed477b9b..34f5a7d671b28caf91553021d43eb6d3b824746c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -191,6 +191,15 @@ void optc2_set_dsc_config(struct timing_generator *optc,
                                        uint32_t dsc_slice_width)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
+       uint32_t data_format = 0;
+       /* skip if dsc mode is not changed */
+       data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL));
+
+       data_format = data_format & 0x30; /* bit5:4 */
+       data_format = data_format >> 4;
+
+       if (data_format == dsc_mode)
+               return;
 
        REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
                OPTC_DSC_MODE, dsc_mode);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c4fa0b9e7138c059ed0e0cef32ffdd94e9c1f979..e2a6e80013f30f26c04f16c0e501ba72b8f8717a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -670,7 +670,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                .max_downscale_src_width = 5120,/*upto 5K*/
                .disable_pplib_wm_range = false,
                .scl_reset_length10 = true,
-               .sanity_checks = true,
+               .sanity_checks = false,
                .disable_tri_buf = true,
 };