pinctrl: mvebu: armada-370: align spi1 clock pin naming
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tue, 9 Jun 2015 16:47:14 +0000 (18:47 +0200)
committerLinus Walleij <linus.walleij@linaro.org>
Wed, 10 Jun 2015 11:59:40 +0000 (13:59 +0200)
Across all SoCs, even on Armada 370 for SPI0, the clock pin uses the
'sck' subname and not 'clk', so this commit adjusts the code and
documentation accordingly.

Since this commit only changes the subname, DT backward compatibility
is not affected.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
drivers/pinctrl/mvebu/pinctrl-armada-370.c

index 3a7dc0e6c94ca089b4987772ed9039c6292d55e6..add7c38ec7d888b958df828139c1847ddc61c7e4 100644 (file)
@@ -18,7 +18,7 @@ mpp1          1        gpo, uart0(txd)
 mpp2          2        gpio, i2c0(sck), uart0(txd)
 mpp3          3        gpio, i2c0(sda), uart0(rxd)
 mpp4          4        gpio, vdd(cpu-pd)
-mpp5          5        gpo, ge0(txclkout), uart1(txd), spi1(clk), audio(mclk)
+mpp5          5        gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)
 mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
 mpp7          7        gpo, ge0(txd1), tdm(dtx), audio(lrclk)
 mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
index fc16ef6e2435dffe01915a9033e9549eac297a22..c2e5e4de49c344d2c0fb9d19477d6a3daaff96a9 100644 (file)
@@ -57,7 +57,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
           MPP_FUNCTION(0x0, "gpo", NULL),
           MPP_FUNCTION(0x1, "ge0", "txclkout"),
           MPP_FUNCTION(0x2, "uart1", "txd"),
-          MPP_FUNCTION(0x4, "spi1", "clk"),
+          MPP_FUNCTION(0x4, "spi1", "sck"),
           MPP_FUNCTION(0x5, "audio", "mclk")),
        MPP_MODE(6,
           MPP_FUNCTION(0x0, "gpio", NULL),