drm/amd/amdgpu: fw version check with gfxoff
authorKenneth Feng <kenneth.feng@amd.com>
Wed, 27 Mar 2019 09:10:09 +0000 (17:10 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 21 Jun 2019 23:59:25 +0000 (18:59 -0500)
1. check the firmware version when enabling gfxoff
2. overwrite the pptable to make sure gfxoff is really
enabled on navi10

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
drivers/gpu/drm/amd/powerplay/navi10_ppt.c

index cc245f4c61ab1e5cd18a48fb68d12e5a4eb272f6..63df59e7335d53bd8c10d2011e0d6175ea692fd1 100644 (file)
@@ -331,7 +331,6 @@ static int smu_set_funcs(struct amdgpu_device *adev)
        switch (adev->asic_type) {
        case CHIP_VEGA20:
        case CHIP_NAVI10:
-               adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
                if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
                        smu->od_enabled = true;
                smu_v11_0_set_smu_funcs(smu);
index 3d3accfcb1489608bbf2af94f33bf777ca235d30..c75da8afe9374bb5c2be09c265a215218c7f40e4 100644 (file)
@@ -117,6 +117,8 @@ static int
 navi10_get_allowed_feature_mask(struct smu_context *smu,
                                  uint32_t *feature_mask, uint32_t num)
 {
+       struct amdgpu_device *adev = smu->adev;
+
        if (num > 2)
                return -EINVAL;
 
@@ -139,6 +141,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
                                | FEATURE_MASK(FEATURE_MMHUB_PG)
                                | FEATURE_MASK(FEATURE_ATHUB_PG);
 
+       if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+               *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
+                               | FEATURE_MASK(FEATURE_GFXOFF_BIT);
+
        return 0;
 }
 
@@ -149,6 +155,7 @@ static int navi10_check_powerplay_table(struct smu_context *smu)
 
 static int navi10_append_powerplay_table(struct smu_context *smu)
 {
+       struct amdgpu_device *adev = smu->adev;
        struct smu_table_context *table_context = &smu->smu_table;
        PPTable_t *smc_pptable = table_context->driver_pptable;
        struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
@@ -234,6 +241,10 @@ static int navi10_append_powerplay_table(struct smu_context *smu)
        /* Mvdd Svi2 Div Ratio Setting */
        smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
 
+       if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+               *(uint64_t *)smc_pptable->FeaturesToRun |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
+                                       | FEATURE_MASK(FEATURE_GFXOFF_BIT);
+
        return 0;
 }