ARM: dts: BCM63xx: fix L2 cache properties

The L2 cache properties were completely off with respect to what the
hardware is configured for. Fix the cache-size, cache-line-size and
cache-sets to reflect the L2 cache controller we have: 512KB, 16 ways
and 32 bytes per cache-line.

Fixes: 46d4bca0445a0 ("ARM: BCM63XX: add BCM63138 minimal Device Tree")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi
index d2d8e94e0aa2042b80dff2d34b49bad66e16345d..f46329c8ad75c00c068e269565bdb1b931083f47 100644 (file)
--- a/arch/arm/boot/dts/bcm63138.dtsi
+++ b/arch/arm/boot/dts/bcm63138.dtsi
@@ -66,8 +66,9 @@
                        reg = <0x1d000 0x1000>;
                        cache-unified;
                        cache-level = <2>;
-                       cache-sets = <16>;
-                       cache-size = <0x80000>;
+                       cache-size = <524288>;
+                       cache-sets = <1024>;
+                       cache-line-size = <32>;
                        interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
                };