drm/amd/display/dc: set num-dwb = 1 as navi10 asic cap
authorhersen wu <hersenxs.wu@amd.com>
Thu, 23 May 2019 22:49:39 +0000 (18:49 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Sat, 22 Jun 2019 14:34:14 +0000 (09:34 -0500)
during navi10 bring up, dwb causes system hang.
to continue debug major issue, disable dwb by
set num-dwb = 0. the hang issue is not reproduced now
by enable num-dwb =1. dc source is shared by all os.
win needs num-dwb = 1.

Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

index 6d9fd93ece8574c8cd1c50ba0f322d4a11b1f79d..c5ac25980f199efd45ef940d442b13a92645b55e 100644 (file)
@@ -661,7 +661,7 @@ static const struct resource_caps res_cap_nv10 = {
                .num_audio = 7,
                .num_stream_encoder = 6,
                .num_pll = 6,
-               .num_dwb = 0,
+               .num_dwb = 1,
                .num_ddc = 6,
                .num_vmid = 16,
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT