--- /dev/null
+From afba5111aed03a05aa7fd46d3d9911319fa87a29 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 30 Jan 2025 16:07:14 +0100
+Subject: [PATCH 1/3] PM: runtime: add of_pm_clk_add_clk_index OP variant
+
+Add of_pm_clk_add_clk_index OP variant of of_pm_clk_add_clk to take as
+argument the clock index in DT instead of the name. This is to handle
+case where clock-names property is not used by the node but clocks are
+referenced with a dt-binding header or internally in the driver.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/base/power/clock_ops.c | 31 +++++++++++++++++++++++++++++++
+ include/linux/pm_clock.h | 1 +
+ 2 files changed, 32 insertions(+)
+
+--- a/drivers/base/power/clock_ops.c
++++ b/drivers/base/power/clock_ops.c
+@@ -259,6 +259,37 @@ int pm_clk_add_clk(struct device *dev, s
+ }
+ EXPORT_SYMBOL_GPL(pm_clk_add_clk);
+
++/**
++ * of_pm_clk_add_clk_index - Start using a device clock for power management.
++ * @dev: Device whose clock is going to be used for power management.
++ * @index: Index of clock that is going to be used for power management.
++ *
++ * Add the clock described in the 'clocks' device-tree node at the index
++ * provided, to the list of clocks used for the power management of @dev.
++ * On success, returns 0. Returns a negative error code if the clock is not
++ * found or cannot be added.
++ */
++int of_pm_clk_add_clk_index(struct device *dev, int index)
++{
++ struct clk *clk;
++ int ret;
++
++ if (!dev || !dev->of_node || index < 0)
++ return -EINVAL;
++
++ clk = of_clk_get(dev->of_node, index);
++ if (IS_ERR(clk))
++ return PTR_ERR(clk);
++
++ ret = pm_clk_add_clk(dev, clk);
++ if (ret) {
++ clk_put(clk);
++ return ret;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(of_pm_clk_add_clk_index);
+
+ /**
+ * of_pm_clk_add_clk - Start using a device clock for power management.
+--- a/include/linux/pm_clock.h
++++ b/include/linux/pm_clock.h
+@@ -41,6 +41,7 @@ extern int pm_clk_create(struct device *
+ extern void pm_clk_destroy(struct device *dev);
+ extern int pm_clk_add(struct device *dev, const char *con_id);
+ extern int pm_clk_add_clk(struct device *dev, struct clk *clk);
++extern int of_pm_clk_add_clk_index(struct device *dev, int index);
+ extern int of_pm_clk_add_clk(struct device *dev, const char *name);
+ extern int of_pm_clk_add_clks(struct device *dev);
+ extern void pm_clk_remove(struct device *dev, const char *con_id);
--- /dev/null
+From 9408076fd9e4d41876af41523cad9bfa77b3a557 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 30 Jan 2025 16:11:14 +0100
+Subject: [PATCH 2/3] clk: qcom: nsscc: Attach required NSSNOC clock to PM
+ domain
+
+There is currently a problem with ICC clock disabling the NSSNOC clock
+as there isn't any user for them on calling sync_state.
+This cause the kernel to stall if NSS is enabled and reboot with the watchdog.
+
+This is caused by the fact that the NSSNOC clock nsscc, snoc and snoc_1
+are actually required to make the NSS work and make the system continue
+booting.
+
+To attach these clock, setup pm-clk in nsscc and setup the correct
+resume/suspend OPs.
+
+With this change, the clock gets correctly attached and are not disabled
+when ICC call the sync_state.
+
+Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/nsscc-ipq9574.c | 49 +++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/nsscc-ipq9574.c
++++ b/drivers/clk/qcom/nsscc-ipq9574.c
+@@ -12,6 +12,8 @@
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <linux/pm_clock.h>
++#include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+ #include <linux/platform_device.h>
+
+@@ -41,6 +43,9 @@ enum {
+ DT_UNIPHY1_NSS_TX_CLK,
+ DT_UNIPHY2_NSS_RX_CLK,
+ DT_UNIPHY2_NSS_TX_CLK,
++ DT_GCC_NSSNOC_NSSCC_CLK,
++ DT_GCC_NSSNOC_SNOC_CLK,
++ DT_GCC_NSSNOC_SNOC_1_CLK,
+ };
+
+ enum {
+@@ -3046,6 +3051,10 @@ static const struct qcom_cc_desc nss_cc_
+ .icc_first_node_id = IPQ_NSSCC_ID,
+ };
+
++static const struct dev_pm_ops nsscc_pm_ops = {
++ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
++};
++
+ static const struct of_device_id nss_cc_ipq9574_match_table[] = {
+ { .compatible = "qcom,ipq9574-nsscc" },
+ { }
+@@ -3054,7 +3063,33 @@ MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_m
+
+ static int nss_cc_ipq9574_probe(struct platform_device *pdev)
+ {
++ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
++ int ret;
++
++ ret = devm_pm_runtime_enable(dev);
++ if (ret)
++ return ret;
++
++ ret = devm_pm_clk_create(dev);
++ if (ret)
++ return ret;
++
++ ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSSNOC_NSSCC_CLK);
++ if (ret)
++ return dev_err_probe(dev, ret,"failed to acquire nssnoc clock\n");
++
++ ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSSNOC_SNOC_CLK);
++ if (ret)
++ return dev_err_probe(dev, ret,"failed to acquire snoc clock\n");
++
++ ret = of_pm_clk_add_clk_index(dev, DT_GCC_NSSNOC_SNOC_1_CLK);
++ if (ret)
++ return dev_err_probe(dev, ret,"failed to acquire snoc_1 clock\n");
++
++ ret = pm_runtime_resume_and_get(dev);
++ if (ret)
++ return ret;
+
+ regmap = qcom_cc_map(pdev, &nss_cc_ipq9574_desc);
+ if (IS_ERR(regmap))
+@@ -3062,7 +3097,18 @@ static int nss_cc_ipq9574_probe(struct p
+
+ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
+
+- return qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap);
++ ret = qcom_cc_really_probe(dev, &nss_cc_ipq9574_desc, regmap);
++ if (ret)
++ goto err_put_pm;
++
++ pm_runtime_put(dev);
++
++ return 0;
++
++err_put_pm:
++ pm_runtime_put_sync(dev);
++
++ return ret;
+ }
+
+ static struct platform_driver nss_cc_ipq9574_driver = {
+@@ -3071,6 +3117,7 @@ static struct platform_driver nss_cc_ipq
+ .name = "qcom,nsscc-ipq9574",
+ .of_match_table = nss_cc_ipq9574_match_table,
+ .sync_state = icc_sync_state,
++ .pm = &nsscc_pm_ops,
+ },
+ };
+
--- /dev/null
+From 893fda72edd2a0b3d92be41af417d315c9c5c253 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 30 Jan 2025 16:23:03 +0100
+Subject: [PATCH 3/3] arm64: dts: qcom: ipq9574: add NSSNOC clock to nss node
+
+Add NSSNOC clock to nss node to attach the clock with PM clock and fix
+the boot stall after ICC sync_state.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+@@ -1250,7 +1250,9 @@
+ <&pcsuniphy1 UNIPHY_NSS_TX_CLK>,
+ <&pcsuniphy2 UNIPHY_NSS_RX_CLK>,
+ <&pcsuniphy2 UNIPHY_NSS_TX_CLK>,
+- <&gcc GCC_NSSCC_CLK>;
++ <&gcc GCC_NSSNOC_NSSCC_CLK>,
++ <&gcc GCC_NSSNOC_SNOC_CLK>,
++ <&gcc GCC_NSSNOC_SNOC_1_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
projects / openwrt / staging / blocktrron.git / commitdiff