ipq806x: reduce PCIe buffer size setting to fix potential data corruption issues
authorFelix Fietkau <nbd@openwrt.org>
Sat, 21 Nov 2015 10:55:05 +0000 (10:55 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Sat, 21 Nov 2015 10:55:05 +0000 (10:55 +0000)
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 47545

target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch
target/linux/ipq806x/patches-4.1/114-pcie-add-ctlr-init.patch

index 11c9810fe276c914a7c058152e34d4e415ff25b6..c0b65c712bb562b807c9186f26aa41aec9785fda 100644 (file)
 +      writel(upper_32_bits(pp->mem_bus_addr),
 +             pcie->dbi + PCIE20_PLR_IATU_UTAR);
 +
-+      /* 1K PCIE buffer setting */
-+      writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
++      /* 256B PCIE buffer setting */
++      writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
 +      writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 +}
 +
index 11c9810fe276c914a7c058152e34d4e415ff25b6..c0b65c712bb562b807c9186f26aa41aec9785fda 100644 (file)
 +      writel(upper_32_bits(pp->mem_bus_addr),
 +             pcie->dbi + PCIE20_PLR_IATU_UTAR);
 +
-+      /* 1K PCIE buffer setting */
-+      writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
++      /* 256B PCIE buffer setting */
++      writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
 +      writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 +}
 +